Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	63167773	13720	0	0
claim_transition_if_regwen_rd_A	63167773	1593	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63167773	13720	0	0
T90	337164	4	0	0
T91	0	3	0	0
T92	0	3	0	0
T93	164185	0	0	0
T103	0	5	0	0
T141	0	5	0	0
T142	0	6	0	0
T143	0	4	0	0
T144	0	1	0	0
T145	0	13	0	0
T146	0	5	0	0
T147	974	0	0	0
T148	41550	0	0	0
T149	7642	0	0	0
T150	1118	0	0	0
T151	55175	0	0	0
T152	5867	0	0	0
T153	25391	0	0	0
T154	47097	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63167773	1593	0	0
T91	503615	17	0	0
T92	0	4	0	0
T94	350831	0	0	0
T107	0	68	0	0
T144	0	9	0	0
T155	0	3	0	0
T156	0	5	0	0
T157	0	19	0	0
T158	0	29	0	0
T159	0	128	0	0
T160	0	493	0	0
T161	52918	0	0	0
T162	7320	0	0	0
T163	982	0	0	0
T164	24128	0	0	0
T165	25463	0	0	0
T166	33926	0	0	0
T167	39541	0	0	0
T168	24765	0	0	0