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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.27 97.92 95.84 93.40 100.00 98.52 98.76 96.47


Total test records in report: 997
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T358 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2377388264 Aug 29 12:15:56 AM UTC 24 Aug 29 12:16:18 AM UTC 24 626919783 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.2429282533 Aug 29 12:15:30 AM UTC 24 Aug 29 12:16:19 AM UTC 24 2291250310 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.2893200888 Aug 29 12:15:53 AM UTC 24 Aug 29 12:16:19 AM UTC 24 912501024 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.432870086 Aug 29 12:14:35 AM UTC 24 Aug 29 12:16:20 AM UTC 24 2572472433 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.1386793501 Aug 29 12:16:11 AM UTC 24 Aug 29 12:16:22 AM UTC 24 459699127 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.80963165 Aug 29 12:16:14 AM UTC 24 Aug 29 12:16:22 AM UTC 24 329591847 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.2755599177 Aug 29 12:16:10 AM UTC 24 Aug 29 12:16:22 AM UTC 24 682129480 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.3418778084 Aug 29 12:16:10 AM UTC 24 Aug 29 12:16:22 AM UTC 24 231369638 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.1791877748 Aug 29 12:16:19 AM UTC 24 Aug 29 12:16:22 AM UTC 24 141178803 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.2711197616 Aug 29 12:16:10 AM UTC 24 Aug 29 12:16:23 AM UTC 24 263198390 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3159124447 Aug 29 12:16:20 AM UTC 24 Aug 29 12:16:23 AM UTC 24 69386714 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.2567986358 Aug 29 12:14:47 AM UTC 24 Aug 29 12:16:23 AM UTC 24 4845538270 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.3375532185 Aug 29 12:17:03 AM UTC 24 Aug 29 12:17:08 AM UTC 24 421543766 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.2881400826 Aug 29 12:16:12 AM UTC 24 Aug 29 12:16:24 AM UTC 24 2040082642 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.893155395 Aug 29 12:16:19 AM UTC 24 Aug 29 12:16:24 AM UTC 24 47437579 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.143049461 Aug 29 12:16:23 AM UTC 24 Aug 29 12:16:27 AM UTC 24 62479238 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.326142221 Aug 29 12:16:14 AM UTC 24 Aug 29 12:16:28 AM UTC 24 1928056111 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.2973547785 Aug 29 12:16:23 AM UTC 24 Aug 29 12:16:29 AM UTC 24 819396869 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.2447966055 Aug 29 12:16:01 AM UTC 24 Aug 29 12:16:32 AM UTC 24 18582328368 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.4124999596 Aug 29 12:16:25 AM UTC 24 Aug 29 12:16:33 AM UTC 24 172452632 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.1274332779 Aug 29 12:16:11 AM UTC 24 Aug 29 12:16:33 AM UTC 24 3387454562 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.3935577680 Aug 29 12:16:14 AM UTC 24 Aug 29 12:16:34 AM UTC 24 780825259 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.1150796215 Aug 29 12:16:23 AM UTC 24 Aug 29 12:16:36 AM UTC 24 356468955 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2232326501 Aug 29 12:16:33 AM UTC 24 Aug 29 12:16:36 AM UTC 24 61294933 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.1617093168 Aug 29 12:16:23 AM UTC 24 Aug 29 12:16:37 AM UTC 24 381482572 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2489485069 Aug 29 12:16:35 AM UTC 24 Aug 29 12:16:37 AM UTC 24 129182854 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.12941484 Aug 29 12:15:42 AM UTC 24 Aug 29 12:16:39 AM UTC 24 10029067644 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.2838920966 Aug 29 12:16:28 AM UTC 24 Aug 29 12:16:39 AM UTC 24 344853356 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.3973660703 Aug 29 12:16:33 AM UTC 24 Aug 29 12:16:39 AM UTC 24 288821964 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.3909460309 Aug 29 12:15:45 AM UTC 24 Aug 29 12:16:39 AM UTC 24 3346982526 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.4155735087 Aug 29 12:16:37 AM UTC 24 Aug 29 12:16:41 AM UTC 24 52012480 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.3709218463 Aug 29 12:16:23 AM UTC 24 Aug 29 12:16:42 AM UTC 24 2495350737 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.3011359840 Aug 29 12:16:25 AM UTC 24 Aug 29 12:16:44 AM UTC 24 1003551760 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.1231860126 Aug 29 12:16:36 AM UTC 24 Aug 29 12:16:45 AM UTC 24 105850533 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.3205160158 Aug 29 12:16:24 AM UTC 24 Aug 29 12:16:46 AM UTC 24 1545530115 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.2602896644 Aug 29 12:16:42 AM UTC 24 Aug 29 12:16:46 AM UTC 24 694983203 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.3358903632 Aug 29 12:16:30 AM UTC 24 Aug 29 12:16:48 AM UTC 24 779841599 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.2800574262 Aug 29 12:16:47 AM UTC 24 Aug 29 12:16:49 AM UTC 24 55474646 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.2032169671 Aug 29 12:16:47 AM UTC 24 Aug 29 12:16:50 AM UTC 24 81573060 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.1041203265 Aug 29 12:15:59 AM UTC 24 Aug 29 12:16:50 AM UTC 24 7174537413 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.3623568950 Aug 29 12:16:08 AM UTC 24 Aug 29 12:16:50 AM UTC 24 1371210312 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.3115949556 Aug 29 12:16:24 AM UTC 24 Aug 29 12:16:51 AM UTC 24 813709886 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.3143838435 Aug 29 12:16:38 AM UTC 24 Aug 29 12:16:51 AM UTC 24 958737889 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.104006088 Aug 29 12:16:38 AM UTC 24 Aug 29 12:16:51 AM UTC 24 302493056 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1842507010 Aug 29 12:16:49 AM UTC 24 Aug 29 12:16:51 AM UTC 24 134424923 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.3421032142 Aug 29 12:16:21 AM UTC 24 Aug 29 12:16:53 AM UTC 24 3003627842 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.3715898277 Aug 29 12:16:44 AM UTC 24 Aug 29 12:16:56 AM UTC 24 319612373 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.135802201 Aug 29 12:16:40 AM UTC 24 Aug 29 12:16:56 AM UTC 24 2370137343 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.2625471322 Aug 29 12:16:42 AM UTC 24 Aug 29 12:16:57 AM UTC 24 249893215 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.3656607755 Aug 29 12:16:52 AM UTC 24 Aug 29 12:16:57 AM UTC 24 388253374 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.2014483410 Aug 29 12:16:37 AM UTC 24 Aug 29 12:16:59 AM UTC 24 603171917 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.796885829 Aug 29 12:16:43 AM UTC 24 Aug 29 12:16:59 AM UTC 24 2279313176 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.3408798470 Aug 29 12:15:56 AM UTC 24 Aug 29 12:16:59 AM UTC 24 1961471770 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.3980517218 Aug 29 12:16:52 AM UTC 24 Aug 29 12:17:00 AM UTC 24 265184991 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.1404854298 Aug 29 12:16:50 AM UTC 24 Aug 29 12:17:00 AM UTC 24 56611904 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.3136045253 Aug 29 12:16:52 AM UTC 24 Aug 29 12:17:02 AM UTC 24 479002143 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.2944751962 Aug 29 12:16:54 AM UTC 24 Aug 29 12:17:02 AM UTC 24 1709087637 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.2196827136 Aug 29 12:16:35 AM UTC 24 Aug 29 12:17:02 AM UTC 24 299245736 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.124002502 Aug 29 12:16:40 AM UTC 24 Aug 29 12:17:02 AM UTC 24 785165409 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2223297808 Aug 29 12:17:00 AM UTC 24 Aug 29 12:17:02 AM UTC 24 26065603 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.2892593276 Aug 29 12:16:12 AM UTC 24 Aug 29 12:17:03 AM UTC 24 2123021742 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2755905928 Aug 29 12:17:01 AM UTC 24 Aug 29 12:17:03 AM UTC 24 34702364 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.3506654215 Aug 29 12:17:01 AM UTC 24 Aug 29 12:17:05 AM UTC 24 29311846 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.828746167 Aug 29 12:16:53 AM UTC 24 Aug 29 12:17:05 AM UTC 24 1511623186 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.3001238641 Aug 29 12:17:03 AM UTC 24 Aug 29 12:17:07 AM UTC 24 44306809 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.1154580859 Aug 29 12:16:57 AM UTC 24 Aug 29 12:17:10 AM UTC 24 1220476193 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.2225936072 Aug 29 12:16:58 AM UTC 24 Aug 29 12:17:11 AM UTC 24 1619247954 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.2158439795 Aug 29 12:16:50 AM UTC 24 Aug 29 12:17:12 AM UTC 24 891495652 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.4074585198 Aug 29 12:16:52 AM UTC 24 Aug 29 12:17:13 AM UTC 24 627843932 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.2588953758 Aug 29 12:17:06 AM UTC 24 Aug 29 12:17:15 AM UTC 24 154093600 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.3669131952 Aug 29 12:16:58 AM UTC 24 Aug 29 12:17:15 AM UTC 24 1229280750 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.3348059709 Aug 29 12:17:13 AM UTC 24 Aug 29 12:17:16 AM UTC 24 17788392 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.2533370631 Aug 29 12:17:08 AM UTC 24 Aug 29 12:17:16 AM UTC 24 1487592066 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.736696458 Aug 29 12:16:24 AM UTC 24 Aug 29 12:17:17 AM UTC 24 1437082642 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.2825660906 Aug 29 12:16:25 AM UTC 24 Aug 29 12:17:17 AM UTC 24 1272145837 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.2105361739 Aug 29 12:16:40 AM UTC 24 Aug 29 12:17:18 AM UTC 24 1575267354 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.2752427577 Aug 29 12:15:12 AM UTC 24 Aug 29 12:17:18 AM UTC 24 12120983976 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.2315565265 Aug 29 12:17:03 AM UTC 24 Aug 29 12:17:18 AM UTC 24 1967579959 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.2243811071 Aug 29 12:16:59 AM UTC 24 Aug 29 12:17:19 AM UTC 24 1068977038 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2208323061 Aug 29 12:17:17 AM UTC 24 Aug 29 12:17:19 AM UTC 24 15558040 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.3848743126 Aug 29 12:16:11 AM UTC 24 Aug 29 12:17:19 AM UTC 24 5291585238 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.4205287053 Aug 29 12:17:16 AM UTC 24 Aug 29 12:17:20 AM UTC 24 63119756 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.3610453130 Aug 29 12:17:05 AM UTC 24 Aug 29 12:17:21 AM UTC 24 1115094689 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3703738921 Aug 29 12:17:04 AM UTC 24 Aug 29 12:17:21 AM UTC 24 3047353171 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.3675386457 Aug 29 12:17:09 AM UTC 24 Aug 29 12:17:22 AM UTC 24 270983980 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.156567824 Aug 29 12:17:18 AM UTC 24 Aug 29 12:17:23 AM UTC 24 632685656 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.3772796162 Aug 29 12:17:57 AM UTC 24 Aug 29 12:18:12 AM UTC 24 210692708 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.1081064166 Aug 29 12:17:20 AM UTC 24 Aug 29 12:17:23 AM UTC 24 50722426 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.2603949551 Aug 29 12:18:07 AM UTC 24 Aug 29 12:18:09 AM UTC 24 16045677 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.1489036742 Aug 29 12:17:04 AM UTC 24 Aug 29 12:17:26 AM UTC 24 1024884898 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.3679692980 Aug 29 12:17:18 AM UTC 24 Aug 29 12:17:26 AM UTC 24 187791813 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.2162402728 Aug 29 12:17:11 AM UTC 24 Aug 29 12:17:26 AM UTC 24 475636742 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.625617321 Aug 29 12:17:18 AM UTC 24 Aug 29 12:17:27 AM UTC 24 681975774 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3504442970 Aug 29 12:17:03 AM UTC 24 Aug 29 12:17:29 AM UTC 24 217782169 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.4091173007 Aug 29 12:17:27 AM UTC 24 Aug 29 12:17:29 AM UTC 24 22515917 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1609280836 Aug 29 12:17:27 AM UTC 24 Aug 29 12:17:29 AM UTC 24 23149452 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.501690329 Aug 29 12:17:11 AM UTC 24 Aug 29 12:17:30 AM UTC 24 6867278195 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.3888822057 Aug 29 12:17:27 AM UTC 24 Aug 29 12:17:30 AM UTC 24 25089162 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.3125696067 Aug 29 12:17:20 AM UTC 24 Aug 29 12:17:31 AM UTC 24 494323841 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.4051093446 Aug 29 12:17:20 AM UTC 24 Aug 29 12:17:33 AM UTC 24 2444340428 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.3684517413 Aug 29 12:17:30 AM UTC 24 Aug 29 12:17:34 AM UTC 24 87943659 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.1084381962 Aug 29 12:17:21 AM UTC 24 Aug 29 12:17:34 AM UTC 24 1598457477 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.1937573765 Aug 29 12:17:20 AM UTC 24 Aug 29 12:17:34 AM UTC 24 1275392961 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.2415552101 Aug 29 12:17:28 AM UTC 24 Aug 29 12:17:35 AM UTC 24 100116423 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.451154862 Aug 29 12:16:02 AM UTC 24 Aug 29 12:17:36 AM UTC 24 2439551701 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.4202775600 Aug 29 12:15:28 AM UTC 24 Aug 29 12:17:37 AM UTC 24 13129363990 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.1925471457 Aug 29 12:17:31 AM UTC 24 Aug 29 12:17:37 AM UTC 24 105659969 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2483227617 Aug 29 12:16:16 AM UTC 24 Aug 29 12:17:37 AM UTC 24 1681765199 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.4000368149 Aug 29 12:17:34 AM UTC 24 Aug 29 12:17:39 AM UTC 24 66707410 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.2440833249 Aug 29 12:17:22 AM UTC 24 Aug 29 12:17:40 AM UTC 24 301581143 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1574398462 Aug 29 12:18:07 AM UTC 24 Aug 29 12:18:09 AM UTC 24 30934456 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.173091239 Aug 29 12:17:38 AM UTC 24 Aug 29 12:17:40 AM UTC 24 199570327 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.228831104 Aug 29 12:17:22 AM UTC 24 Aug 29 12:17:41 AM UTC 24 649573832 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.1859146511 Aug 29 12:17:30 AM UTC 24 Aug 29 12:17:41 AM UTC 24 717191103 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.4056241728 Aug 29 12:17:40 AM UTC 24 Aug 29 12:17:43 AM UTC 24 26553997 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.4075163265 Aug 29 12:17:21 AM UTC 24 Aug 29 12:17:43 AM UTC 24 2412124726 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.838351991 Aug 29 12:17:17 AM UTC 24 Aug 29 12:17:44 AM UTC 24 580081082 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.2518512993 Aug 29 12:16:53 AM UTC 24 Aug 29 12:17:44 AM UTC 24 1542008002 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3784514567 Aug 29 12:17:41 AM UTC 24 Aug 29 12:17:44 AM UTC 24 14926936 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.585999543 Aug 29 12:17:30 AM UTC 24 Aug 29 12:17:46 AM UTC 24 1306227059 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.578278901 Aug 29 12:17:43 AM UTC 24 Aug 29 12:17:47 AM UTC 24 144932341 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.3541398421 Aug 29 12:17:28 AM UTC 24 Aug 29 12:17:47 AM UTC 24 228663135 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.3715620502 Aug 29 12:17:32 AM UTC 24 Aug 29 12:18:10 AM UTC 24 831314826 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.2487253696 Aug 29 12:17:41 AM UTC 24 Aug 29 12:17:48 AM UTC 24 108820824 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.1703384566 Aug 29 12:17:44 AM UTC 24 Aug 29 12:17:51 AM UTC 24 1610976966 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.1600567325 Aug 29 12:17:38 AM UTC 24 Aug 29 12:17:53 AM UTC 24 887665951 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.1114244261 Aug 29 12:17:36 AM UTC 24 Aug 29 12:17:54 AM UTC 24 513566465 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.1982104715 Aug 29 12:17:52 AM UTC 24 Aug 29 12:17:55 AM UTC 24 30688265 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.3758853957 Aug 29 12:17:43 AM UTC 24 Aug 29 12:17:55 AM UTC 24 944652999 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.680028558 Aug 29 12:17:35 AM UTC 24 Aug 29 12:17:56 AM UTC 24 2966995788 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.1405644144 Aug 29 12:17:35 AM UTC 24 Aug 29 12:17:56 AM UTC 24 1356109237 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.4127899584 Aug 29 12:17:55 AM UTC 24 Aug 29 12:17:57 AM UTC 24 11153627 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.1663630489 Aug 29 12:17:54 AM UTC 24 Aug 29 12:17:58 AM UTC 24 87893041 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.574458536 Aug 29 12:17:57 AM UTC 24 Aug 29 12:18:01 AM UTC 24 33030401 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.1076711348 Aug 29 12:17:48 AM UTC 24 Aug 29 12:18:02 AM UTC 24 278010157 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.1064096435 Aug 29 12:17:47 AM UTC 24 Aug 29 12:18:04 AM UTC 24 1720786797 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.1516691859 Aug 29 12:17:04 AM UTC 24 Aug 29 12:18:05 AM UTC 24 6905766013 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.531288777 Aug 29 12:17:45 AM UTC 24 Aug 29 12:18:05 AM UTC 24 1617980926 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.3048027809 Aug 29 12:17:45 AM UTC 24 Aug 29 12:18:05 AM UTC 24 1072824777 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.4212410196 Aug 29 12:17:48 AM UTC 24 Aug 29 12:18:06 AM UTC 24 230293150 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.1708738289 Aug 29 12:17:43 AM UTC 24 Aug 29 12:18:06 AM UTC 24 1902168767 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.1608979680 Aug 29 12:16:56 AM UTC 24 Aug 29 12:18:06 AM UTC 24 9850559232 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.906848918 Aug 29 12:15:05 AM UTC 24 Aug 29 12:18:07 AM UTC 24 22934401639 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.372331968 Aug 29 12:17:56 AM UTC 24 Aug 29 12:18:07 AM UTC 24 659623842 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.2694443393 Aug 29 12:17:41 AM UTC 24 Aug 29 12:18:11 AM UTC 24 314910822 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.1986366872 Aug 29 12:18:07 AM UTC 24 Aug 29 12:18:12 AM UTC 24 229232548 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.4049929211 Aug 29 12:17:58 AM UTC 24 Aug 29 12:18:13 AM UTC 24 962915545 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.350376370 Aug 29 12:18:10 AM UTC 24 Aug 29 12:18:14 AM UTC 24 466283959 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.3828493187 Aug 29 12:18:08 AM UTC 24 Aug 29 12:18:15 AM UTC 24 134017503 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.1993137303 Aug 29 12:17:07 AM UTC 24 Aug 29 12:18:16 AM UTC 24 2091486754 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.4205245596 Aug 29 12:17:45 AM UTC 24 Aug 29 12:18:16 AM UTC 24 1131809899 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1317332962 Aug 29 12:18:01 AM UTC 24 Aug 29 12:18:17 AM UTC 24 1364967712 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.213401473 Aug 29 12:18:14 AM UTC 24 Aug 29 12:18:17 AM UTC 24 19203385 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3666716321 Aug 29 12:15:38 AM UTC 24 Aug 29 12:18:17 AM UTC 24 6364691229 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.750925022 Aug 29 12:18:07 AM UTC 24 Aug 29 12:18:18 AM UTC 24 320406159 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.953528947 Aug 29 12:18:15 AM UTC 24 Aug 29 12:18:18 AM UTC 24 15716166 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.4018834199 Aug 29 12:18:04 AM UTC 24 Aug 29 12:18:19 AM UTC 24 1016087722 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.3002210701 Aug 29 12:18:14 AM UTC 24 Aug 29 12:18:19 AM UTC 24 94003970 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.2716426948 Aug 29 12:18:09 AM UTC 24 Aug 29 12:18:21 AM UTC 24 1017434592 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.402907745 Aug 29 12:17:59 AM UTC 24 Aug 29 12:18:21 AM UTC 24 2224265628 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.1794903761 Aug 29 12:17:35 AM UTC 24 Aug 29 12:18:22 AM UTC 24 2226898286 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.3510503594 Aug 29 12:18:10 AM UTC 24 Aug 29 12:18:22 AM UTC 24 2067136963 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.2520168585 Aug 29 12:18:18 AM UTC 24 Aug 29 12:18:23 AM UTC 24 531786864 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1574300142 Aug 29 12:18:08 AM UTC 24 Aug 29 12:18:24 AM UTC 24 2653204856 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.170556196 Aug 29 12:16:40 AM UTC 24 Aug 29 12:18:24 AM UTC 24 6210723395 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2760083370 Aug 29 12:18:07 AM UTC 24 Aug 29 12:18:55 AM UTC 24 14876482983 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.15316180 Aug 29 12:18:12 AM UTC 24 Aug 29 12:18:24 AM UTC 24 1397208103 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1362426286 Aug 29 12:18:20 AM UTC 24 Aug 29 12:18:24 AM UTC 24 141256072 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.627521189 Aug 29 12:18:12 AM UTC 24 Aug 29 12:18:25 AM UTC 24 532550047 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.539328249 Aug 29 12:18:03 AM UTC 24 Aug 29 12:18:25 AM UTC 24 2456326427 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.707284457 Aug 29 12:18:23 AM UTC 24 Aug 29 12:18:26 AM UTC 24 32604215 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.834429031 Aug 29 12:18:23 AM UTC 24 Aug 29 12:18:26 AM UTC 24 57514992 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.803270387 Aug 29 12:17:56 AM UTC 24 Aug 29 12:18:27 AM UTC 24 1056133054 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.494725082 Aug 29 12:17:38 AM UTC 24 Aug 29 12:18:28 AM UTC 24 2807910592 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.1596576159 Aug 29 12:18:20 AM UTC 24 Aug 29 12:18:28 AM UTC 24 3329793692 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.3496819149 Aug 29 12:18:18 AM UTC 24 Aug 29 12:18:28 AM UTC 24 65961835 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.1833628494 Aug 29 12:17:48 AM UTC 24 Aug 29 12:18:28 AM UTC 24 1512739049 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.3244760667 Aug 29 12:14:25 AM UTC 24 Aug 29 12:18:29 AM UTC 24 6384287893 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.450557200 Aug 29 12:18:23 AM UTC 24 Aug 29 12:18:29 AM UTC 24 45624605 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.1600073928 Aug 29 12:18:28 AM UTC 24 Aug 29 12:18:30 AM UTC 24 69274225 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.1335278960 Aug 29 12:18:20 AM UTC 24 Aug 29 12:18:31 AM UTC 24 1130184064 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.1472043128 Aug 29 12:17:32 AM UTC 24 Aug 29 12:18:31 AM UTC 24 3313909212 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.666842952 Aug 29 12:17:21 AM UTC 24 Aug 29 12:18:32 AM UTC 24 3986845155 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.1718567199 Aug 29 12:18:25 AM UTC 24 Aug 29 12:18:32 AM UTC 24 77549596 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.1050743989 Aug 29 12:18:20 AM UTC 24 Aug 29 12:18:32 AM UTC 24 366559314 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.775871468 Aug 29 12:18:30 AM UTC 24 Aug 29 12:18:32 AM UTC 24 47024530 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.825528628 Aug 29 12:18:30 AM UTC 24 Aug 29 12:18:33 AM UTC 24 22277400 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.1610476403 Aug 29 12:18:30 AM UTC 24 Aug 29 12:18:34 AM UTC 24 59235194 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.1402580519 Aug 29 12:18:18 AM UTC 24 Aug 29 12:18:35 AM UTC 24 335848099 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.1172598771 Aug 29 12:18:07 AM UTC 24 Aug 29 12:18:36 AM UTC 24 245630139 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.701797644 Aug 29 12:18:25 AM UTC 24 Aug 29 12:18:36 AM UTC 24 863913843 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.1128346793 Aug 29 12:18:20 AM UTC 24 Aug 29 12:18:37 AM UTC 24 592975079 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.2300445089 Aug 29 12:18:35 AM UTC 24 Aug 29 12:18:37 AM UTC 24 74312344 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.2048721289 Aug 29 12:18:27 AM UTC 24 Aug 29 12:18:38 AM UTC 24 641466243 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1856005932 Aug 29 12:17:44 AM UTC 24 Aug 29 12:18:39 AM UTC 24 5473439643 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.4265377425 Aug 29 12:18:37 AM UTC 24 Aug 29 12:18:39 AM UTC 24 12843693 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.684419131 Aug 29 12:18:36 AM UTC 24 Aug 29 12:18:40 AM UTC 24 286795243 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.910345354 Aug 29 12:18:25 AM UTC 24 Aug 29 12:18:41 AM UTC 24 489962109 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.765199400 Aug 29 12:18:30 AM UTC 24 Aug 29 12:18:41 AM UTC 24 91464015 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.1604445500 Aug 29 12:18:27 AM UTC 24 Aug 29 12:18:42 AM UTC 24 633355080 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.2795303515 Aug 29 12:18:25 AM UTC 24 Aug 29 12:18:42 AM UTC 24 2534242277 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.497028386 Aug 29 12:18:27 AM UTC 24 Aug 29 12:18:42 AM UTC 24 1080069142 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3038326457 Aug 29 12:18:34 AM UTC 24 Aug 29 12:18:43 AM UTC 24 1036656864 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.105019054 Aug 29 12:18:34 AM UTC 24 Aug 29 12:18:43 AM UTC 24 870930719 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.2019098728 Aug 29 12:18:38 AM UTC 24 Aug 29 12:18:44 AM UTC 24 360396594 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.3261394608 Aug 29 12:18:44 AM UTC 24 Aug 29 12:18:46 AM UTC 24 234300499 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3273550740 Aug 29 12:18:44 AM UTC 24 Aug 29 12:18:46 AM UTC 24 12983589 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.1578787449 Aug 29 12:18:44 AM UTC 24 Aug 29 12:18:47 AM UTC 24 52573532 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.1352183213 Aug 29 12:18:17 AM UTC 24 Aug 29 12:18:48 AM UTC 24 1207816911 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.2807159130 Aug 29 12:18:25 AM UTC 24 Aug 29 12:18:49 AM UTC 24 654359147 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.1425885800 Aug 29 12:18:32 AM UTC 24 Aug 29 12:18:50 AM UTC 24 1243311985 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.3634626933 Aug 29 12:18:32 AM UTC 24 Aug 29 12:18:50 AM UTC 24 1398465191 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.1202585318 Aug 29 12:18:32 AM UTC 24 Aug 29 12:18:50 AM UTC 24 876895466 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.1311843979 Aug 29 12:18:37 AM UTC 24 Aug 29 12:18:51 AM UTC 24 45287205 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3618031849 Aug 29 12:18:53 AM UTC 24 Aug 29 12:18:56 AM UTC 24 12310742 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.1167088224 Aug 29 12:15:50 AM UTC 24 Aug 29 12:18:51 AM UTC 24 5917729684 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.2178180248 Aug 29 12:18:47 AM UTC 24 Aug 29 12:18:52 AM UTC 24 57869796 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.1945609810 Aug 29 12:18:49 AM UTC 24 Aug 29 12:18:52 AM UTC 24 29158798 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2505961043 Aug 29 12:17:00 AM UTC 24 Aug 29 12:18:52 AM UTC 24 9650799138 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.1341886807 Aug 29 12:18:47 AM UTC 24 Aug 29 12:18:52 AM UTC 24 67425800 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.3329359496 Aug 29 12:18:30 AM UTC 24 Aug 29 12:18:54 AM UTC 24 494208747 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.2305548283 Aug 29 12:18:40 AM UTC 24 Aug 29 12:18:53 AM UTC 24 2078069497 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.2301069136 Aug 29 12:18:41 AM UTC 24 Aug 29 12:18:53 AM UTC 24 657659657 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.570537341 Aug 29 12:18:25 AM UTC 24 Aug 29 12:18:53 AM UTC 24 263912815 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.512151313 Aug 29 12:18:33 AM UTC 24 Aug 29 12:18:54 AM UTC 24 326596595 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.3003961361 Aug 29 12:18:53 AM UTC 24 Aug 29 12:18:56 AM UTC 24 75001610 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.3175106677 Aug 29 12:18:42 AM UTC 24 Aug 29 12:18:56 AM UTC 24 615787917 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.2434681973 Aug 29 12:18:53 AM UTC 24 Aug 29 12:18:57 AM UTC 24 201447225 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.2294110923 Aug 29 12:18:41 AM UTC 24 Aug 29 12:18:57 AM UTC 24 1545256281 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.3098985557 Aug 29 12:18:49 AM UTC 24 Aug 29 12:18:58 AM UTC 24 469948738 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.3970310535 Aug 29 12:18:42 AM UTC 24 Aug 29 12:18:58 AM UTC 24 978870137 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.1132183402 Aug 29 12:18:55 AM UTC 24 Aug 29 12:18:59 AM UTC 24 152992133 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.4003110297 Aug 29 12:18:55 AM UTC 24 Aug 29 12:18:59 AM UTC 24 74368944 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.193505875 Aug 29 12:18:57 AM UTC 24 Aug 29 12:19:00 AM UTC 24 34350295 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.969433293 Aug 29 12:18:57 AM UTC 24 Aug 29 12:19:01 AM UTC 24 35363758 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.4260036033 Aug 29 12:18:59 AM UTC 24 Aug 29 12:19:01 AM UTC 24 15471625 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.888482054 Aug 29 12:18:53 AM UTC 24 Aug 29 12:19:02 AM UTC 24 362793793 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.20610514 Aug 29 12:18:39 AM UTC 24 Aug 29 12:19:03 AM UTC 24 2351376895 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.3161248001 Aug 29 12:18:51 AM UTC 24 Aug 29 12:19:03 AM UTC 24 1539341570 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2232321114 Aug 29 12:18:50 AM UTC 24 Aug 29 12:19:04 AM UTC 24 706304955 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.2925032636 Aug 29 12:18:59 AM UTC 24 Aug 29 12:19:05 AM UTC 24 295200988 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.1506847343 Aug 29 12:18:48 AM UTC 24 Aug 29 12:19:06 AM UTC 24 1190631095 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.2568025545 Aug 29 12:19:02 AM UTC 24 Aug 29 12:19:07 AM UTC 24 3279656472 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.2079699095 Aug 29 12:19:06 AM UTC 24 Aug 29 12:19:08 AM UTC 24 45996927 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.3335829791 Aug 29 12:18:55 AM UTC 24 Aug 29 12:19:08 AM UTC 24 280878391 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.296121182 Aug 29 12:18:51 AM UTC 24 Aug 29 12:19:08 AM UTC 24 1939892578 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.3013788592 Aug 29 12:18:59 AM UTC 24 Aug 29 12:19:10 AM UTC 24 387687844 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.2845238665 Aug 29 12:18:55 AM UTC 24 Aug 29 12:19:10 AM UTC 24 284575918 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1356204833 Aug 29 12:18:22 AM UTC 24 Aug 29 12:19:10 AM UTC 24 1708054873 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.4050685899 Aug 29 12:18:37 AM UTC 24 Aug 29 12:19:10 AM UTC 24 1221168143 ps
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