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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.27 97.92 95.84 93.40 100.00 98.52 98.76 96.47


Total test records in report: 997
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T597 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2974688017 Aug 29 12:19:08 AM UTC 24 Aug 29 12:19:10 AM UTC 24 21565028 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.1029564122 Aug 29 12:18:55 AM UTC 24 Aug 29 12:19:11 AM UTC 24 576145300 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1280337488 Aug 29 12:18:56 AM UTC 24 Aug 29 12:19:12 AM UTC 24 675688849 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.902589675 Aug 29 12:19:07 AM UTC 24 Aug 29 12:19:13 AM UTC 24 73415829 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.2391014197 Aug 29 12:18:55 AM UTC 24 Aug 29 12:19:13 AM UTC 24 1571235577 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3177231230 Aug 29 12:19:03 AM UTC 24 Aug 29 12:19:14 AM UTC 24 1356446280 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.2476252674 Aug 29 12:19:10 AM UTC 24 Aug 29 12:19:15 AM UTC 24 67612700 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.3361859117 Aug 29 12:19:10 AM UTC 24 Aug 29 12:19:15 AM UTC 24 295874450 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.3458634705 Aug 29 12:19:00 AM UTC 24 Aug 29 12:19:16 AM UTC 24 380649570 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.1543059496 Aug 29 12:19:14 AM UTC 24 Aug 29 12:19:16 AM UTC 24 29157819 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3596948559 Aug 29 12:17:12 AM UTC 24 Aug 29 12:19:17 AM UTC 24 13161350476 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.416164400 Aug 29 12:19:01 AM UTC 24 Aug 29 12:19:18 AM UTC 24 261773662 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3927856823 Aug 29 12:19:15 AM UTC 24 Aug 29 12:19:18 AM UTC 24 32882609 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.2331503175 Aug 29 12:19:14 AM UTC 24 Aug 29 12:19:18 AM UTC 24 28128058 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.2076839719 Aug 29 12:18:45 AM UTC 24 Aug 29 12:19:19 AM UTC 24 230635674 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.2820523055 Aug 29 12:18:53 AM UTC 24 Aug 29 12:19:20 AM UTC 24 847721213 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.4241234633 Aug 29 12:19:17 AM UTC 24 Aug 29 12:19:20 AM UTC 24 15225194 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3915009693 Aug 29 12:19:25 AM UTC 24 Aug 29 12:19:42 AM UTC 24 1009606510 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.774869745 Aug 29 12:17:49 AM UTC 24 Aug 29 12:19:21 AM UTC 24 3037559312 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.304945287 Aug 29 12:19:19 AM UTC 24 Aug 29 12:19:22 AM UTC 24 400205994 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.3633048466 Aug 29 12:19:11 AM UTC 24 Aug 29 12:19:22 AM UTC 24 5013300200 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.3068955786 Aug 29 12:15:01 AM UTC 24 Aug 29 12:19:22 AM UTC 24 6730306125 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.3185518783 Aug 29 12:19:03 AM UTC 24 Aug 29 12:19:23 AM UTC 24 368220084 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2111522940 Aug 29 12:19:21 AM UTC 24 Aug 29 12:19:24 AM UTC 24 61694834 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.526834510 Aug 29 12:19:12 AM UTC 24 Aug 29 12:19:24 AM UTC 24 409474489 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1383931197 Aug 29 12:19:23 AM UTC 24 Aug 29 12:19:25 AM UTC 24 13057586 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.133070613 Aug 29 12:19:16 AM UTC 24 Aug 29 12:19:26 AM UTC 24 400147087 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2926042986 Aug 29 12:19:23 AM UTC 24 Aug 29 12:19:27 AM UTC 24 47601447 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.776789823 Aug 29 12:19:10 AM UTC 24 Aug 29 12:19:27 AM UTC 24 235509639 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.502436095 Aug 29 12:19:13 AM UTC 24 Aug 29 12:19:27 AM UTC 24 314069425 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.2271386703 Aug 29 12:18:59 AM UTC 24 Aug 29 12:19:28 AM UTC 24 238447382 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.2841630703 Aug 29 12:19:19 AM UTC 24 Aug 29 12:19:28 AM UTC 24 676407595 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.3508906536 Aug 29 12:16:30 AM UTC 24 Aug 29 12:19:28 AM UTC 24 7496513048 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.477429493 Aug 29 12:19:24 AM UTC 24 Aug 29 12:19:29 AM UTC 24 39487188 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.2707661866 Aug 29 12:19:11 AM UTC 24 Aug 29 12:19:29 AM UTC 24 322539802 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.808637510 Aug 29 12:19:17 AM UTC 24 Aug 29 12:19:29 AM UTC 24 535197127 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.218465008 Aug 29 12:19:19 AM UTC 24 Aug 29 12:19:32 AM UTC 24 266345791 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4146337702 Aug 29 12:19:30 AM UTC 24 Aug 29 12:19:32 AM UTC 24 109572642 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.1790128311 Aug 29 12:17:20 AM UTC 24 Aug 29 12:19:33 AM UTC 24 13362871798 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.389582173 Aug 29 12:19:30 AM UTC 24 Aug 29 12:19:33 AM UTC 24 69824474 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.1566827325 Aug 29 12:19:30 AM UTC 24 Aug 29 12:19:33 AM UTC 24 20118905 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.2140608694 Aug 29 12:19:24 AM UTC 24 Aug 29 12:19:34 AM UTC 24 45712812 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.837926478 Aug 29 12:19:34 AM UTC 24 Aug 29 12:19:41 AM UTC 24 251222250 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3314317565 Aug 29 12:17:00 AM UTC 24 Aug 29 12:19:35 AM UTC 24 3970862456 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.4075995841 Aug 29 12:19:27 AM UTC 24 Aug 29 12:19:37 AM UTC 24 223369071 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.2246721219 Aug 29 12:19:20 AM UTC 24 Aug 29 12:19:37 AM UTC 24 667337563 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.2826911792 Aug 29 12:19:02 AM UTC 24 Aug 29 12:19:38 AM UTC 24 851919515 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.1695737000 Aug 29 12:19:33 AM UTC 24 Aug 29 12:19:38 AM UTC 24 181786035 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.1154056659 Aug 29 12:19:19 AM UTC 24 Aug 29 12:19:38 AM UTC 24 480009479 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.3283817240 Aug 29 12:19:11 AM UTC 24 Aug 29 12:19:39 AM UTC 24 2835326296 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.140808887 Aug 29 12:18:34 AM UTC 24 Aug 29 12:19:39 AM UTC 24 3039227559 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.511393417 Aug 29 12:18:27 AM UTC 24 Aug 29 12:19:40 AM UTC 24 4397122897 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.1829246117 Aug 29 12:19:28 AM UTC 24 Aug 29 12:19:40 AM UTC 24 754922357 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.2330808501 Aug 29 12:19:33 AM UTC 24 Aug 29 12:19:40 AM UTC 24 382374347 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.2445922872 Aug 29 12:19:38 AM UTC 24 Aug 29 12:19:41 AM UTC 24 12900197 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.4140746952 Aug 29 12:19:40 AM UTC 24 Aug 29 12:19:42 AM UTC 24 17369891 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.4222062910 Aug 29 12:19:28 AM UTC 24 Aug 29 12:19:43 AM UTC 24 994794119 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.2054612166 Aug 29 12:20:19 AM UTC 24 Aug 29 12:20:22 AM UTC 24 97625635 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.3657768825 Aug 29 12:19:40 AM UTC 24 Aug 29 12:19:44 AM UTC 24 382162522 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.3419829437 Aug 29 12:19:28 AM UTC 24 Aug 29 12:19:45 AM UTC 24 1965935642 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.2163326643 Aug 29 12:19:36 AM UTC 24 Aug 29 12:19:45 AM UTC 24 630478127 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.3229192100 Aug 29 12:19:42 AM UTC 24 Aug 29 12:19:45 AM UTC 24 103335285 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.1282278791 Aug 29 12:19:34 AM UTC 24 Aug 29 12:19:46 AM UTC 24 928371440 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.1625655777 Aug 29 12:19:45 AM UTC 24 Aug 29 12:19:47 AM UTC 24 14861304 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.2029090772 Aug 29 12:19:10 AM UTC 24 Aug 29 12:19:47 AM UTC 24 265894014 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.1210534227 Aug 29 12:19:27 AM UTC 24 Aug 29 12:19:47 AM UTC 24 421000150 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.2955040763 Aug 29 12:20:15 AM UTC 24 Aug 29 12:20:23 AM UTC 24 262135909 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.1584752023 Aug 29 12:19:34 AM UTC 24 Aug 29 12:19:48 AM UTC 24 411075545 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.1649113429 Aug 29 12:19:16 AM UTC 24 Aug 29 12:19:48 AM UTC 24 545586478 ps
T663 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.426716961 Aug 29 12:19:41 AM UTC 24 Aug 29 12:19:48 AM UTC 24 235033548 ps
T664 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1036651861 Aug 29 12:19:46 AM UTC 24 Aug 29 12:19:48 AM UTC 24 110396842 ps
T665 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.4286663897 Aug 29 12:19:41 AM UTC 24 Aug 29 12:19:49 AM UTC 24 260000827 ps
T666 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.968577928 Aug 29 12:19:46 AM UTC 24 Aug 29 12:19:52 AM UTC 24 55903170 ps
T667 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2236055341 Aug 29 12:19:43 AM UTC 24 Aug 29 12:19:52 AM UTC 24 292125038 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.2981623720 Aug 29 12:19:50 AM UTC 24 Aug 29 12:19:53 AM UTC 24 19028649 ps
T668 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.2880378214 Aug 29 12:19:37 AM UTC 24 Aug 29 12:19:53 AM UTC 24 5610298027 ps
T669 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.327458983 Aug 29 12:19:35 AM UTC 24 Aug 29 12:19:53 AM UTC 24 4415444397 ps
T670 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3401076926 Aug 29 12:19:51 AM UTC 24 Aug 29 12:19:54 AM UTC 24 13542711 ps
T671 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.4082030711 Aug 29 12:19:48 AM UTC 24 Aug 29 12:19:54 AM UTC 24 163483628 ps
T672 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.737862667 Aug 29 12:19:42 AM UTC 24 Aug 29 12:19:55 AM UTC 24 1211273444 ps
T673 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.2296561296 Aug 29 12:20:56 AM UTC 24 Aug 29 12:21:15 AM UTC 24 578615902 ps
T674 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.3399183242 Aug 29 12:19:43 AM UTC 24 Aug 29 12:19:56 AM UTC 24 254839455 ps
T675 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.772751105 Aug 29 12:19:50 AM UTC 24 Aug 29 12:19:56 AM UTC 24 1129051581 ps
T676 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.1052607576 Aug 29 12:19:48 AM UTC 24 Aug 29 12:19:56 AM UTC 24 401383755 ps
T677 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.876801631 Aug 29 12:19:51 AM UTC 24 Aug 29 12:19:56 AM UTC 24 79624668 ps
T678 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.1925579556 Aug 29 12:19:24 AM UTC 24 Aug 29 12:19:57 AM UTC 24 828723020 ps
T679 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.108525566 Aug 29 12:19:54 AM UTC 24 Aug 29 12:19:57 AM UTC 24 41365090 ps
T680 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.3620949540 Aug 29 12:16:46 AM UTC 24 Aug 29 12:19:58 AM UTC 24 79772382387 ps
T681 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.1394021054 Aug 29 12:19:42 AM UTC 24 Aug 29 12:19:58 AM UTC 24 412174157 ps
T682 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.2999742125 Aug 29 12:19:50 AM UTC 24 Aug 29 12:19:58 AM UTC 24 442692304 ps
T683 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.1236172863 Aug 29 12:19:54 AM UTC 24 Aug 29 12:19:59 AM UTC 24 762352794 ps
T684 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.2442217846 Aug 29 12:19:41 AM UTC 24 Aug 29 12:19:59 AM UTC 24 1511943305 ps
T685 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.1718485291 Aug 29 12:19:57 AM UTC 24 Aug 29 12:19:59 AM UTC 24 40865964 ps
T686 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.3565717213 Aug 29 12:19:54 AM UTC 24 Aug 29 12:20:00 AM UTC 24 3087676361 ps
T687 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3837350144 Aug 29 12:19:58 AM UTC 24 Aug 29 12:20:01 AM UTC 24 17538426 ps
T688 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.3779173482 Aug 29 12:18:13 AM UTC 24 Aug 29 12:20:01 AM UTC 24 8671056930 ps
T689 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.3069948363 Aug 29 12:19:58 AM UTC 24 Aug 29 12:20:02 AM UTC 24 36454947 ps
T690 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.1388421448 Aug 29 12:19:31 AM UTC 24 Aug 29 12:20:02 AM UTC 24 1048798406 ps
T691 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.309146801 Aug 29 12:19:50 AM UTC 24 Aug 29 12:20:03 AM UTC 24 905747917 ps
T692 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.511961558 Aug 29 12:19:40 AM UTC 24 Aug 29 12:20:03 AM UTC 24 451152034 ps
T693 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.2497087336 Aug 29 12:20:00 AM UTC 24 Aug 29 12:20:05 AM UTC 24 109525104 ps
T694 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.734677162 Aug 29 12:19:50 AM UTC 24 Aug 29 12:20:06 AM UTC 24 1043556743 ps
T695 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.4040318377 Aug 29 12:19:50 AM UTC 24 Aug 29 12:20:06 AM UTC 24 819083392 ps
T696 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.164883749 Aug 29 12:20:05 AM UTC 24 Aug 29 12:20:07 AM UTC 24 31592569 ps
T697 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2960490515 Aug 29 12:20:04 AM UTC 24 Aug 29 12:20:07 AM UTC 24 34623307 ps
T698 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.3942396706 Aug 29 12:20:04 AM UTC 24 Aug 29 12:20:07 AM UTC 24 164034646 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.3963866547 Aug 29 12:18:56 AM UTC 24 Aug 29 12:20:08 AM UTC 24 1971344329 ps
T699 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.2497214031 Aug 29 12:20:00 AM UTC 24 Aug 29 12:20:08 AM UTC 24 290008261 ps
T700 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.4233138652 Aug 29 12:19:55 AM UTC 24 Aug 29 12:20:08 AM UTC 24 262201638 ps
T701 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2238128283 Aug 29 12:19:54 AM UTC 24 Aug 29 12:20:08 AM UTC 24 424866796 ps
T702 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.3107072378 Aug 29 12:19:57 AM UTC 24 Aug 29 12:20:10 AM UTC 24 317445418 ps
T703 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.2252739064 Aug 29 12:19:48 AM UTC 24 Aug 29 12:20:10 AM UTC 24 375467401 ps
T704 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1022976202 Aug 29 12:20:07 AM UTC 24 Aug 29 12:20:11 AM UTC 24 69861037 ps
T705 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.865306272 Aug 29 12:20:00 AM UTC 24 Aug 29 12:20:11 AM UTC 24 333845171 ps
T706 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.872207878 Aug 29 12:20:01 AM UTC 24 Aug 29 12:20:12 AM UTC 24 2069454627 ps
T707 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.3540338202 Aug 29 12:20:07 AM UTC 24 Aug 29 12:20:13 AM UTC 24 159862010 ps
T708 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.3810008565 Aug 29 12:20:11 AM UTC 24 Aug 29 12:20:13 AM UTC 24 45314193 ps
T709 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.235089760 Aug 29 12:19:55 AM UTC 24 Aug 29 12:20:13 AM UTC 24 367285018 ps
T710 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.3460693045 Aug 29 12:20:00 AM UTC 24 Aug 29 12:20:14 AM UTC 24 962942852 ps
T711 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3332832777 Aug 29 12:20:12 AM UTC 24 Aug 29 12:20:14 AM UTC 24 34440571 ps
T712 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.241643804 Aug 29 12:20:00 AM UTC 24 Aug 29 12:20:15 AM UTC 24 547068388 ps
T713 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.3573477730 Aug 29 12:19:54 AM UTC 24 Aug 29 12:20:15 AM UTC 24 2007002871 ps
T714 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.2663194104 Aug 29 12:20:08 AM UTC 24 Aug 29 12:20:16 AM UTC 24 1709780383 ps
T715 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.952487100 Aug 29 12:20:08 AM UTC 24 Aug 29 12:20:24 AM UTC 24 367959417 ps
T716 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.1567471307 Aug 29 12:20:12 AM UTC 24 Aug 29 12:20:16 AM UTC 24 32008464 ps
T717 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.497595552 Aug 29 12:20:03 AM UTC 24 Aug 29 12:20:17 AM UTC 24 291800179 ps
T718 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.2306279131 Aug 29 12:19:53 AM UTC 24 Aug 29 12:20:18 AM UTC 24 354379754 ps
T719 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.2949587773 Aug 29 12:20:15 AM UTC 24 Aug 29 12:20:18 AM UTC 24 31124759 ps
T720 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.3413675439 Aug 29 12:18:34 AM UTC 24 Aug 29 12:20:19 AM UTC 24 6724124069 ps
T721 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3286044485 Aug 29 12:18:43 AM UTC 24 Aug 29 12:20:19 AM UTC 24 3160435030 ps
T722 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.2521548083 Aug 29 12:20:17 AM UTC 24 Aug 29 12:20:20 AM UTC 24 89661088 ps
T723 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.3885265988 Aug 29 12:20:01 AM UTC 24 Aug 29 12:20:20 AM UTC 24 724781390 ps
T724 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.682360983 Aug 29 12:19:47 AM UTC 24 Aug 29 12:20:20 AM UTC 24 2464224477 ps
T725 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2236153173 Aug 29 12:20:19 AM UTC 24 Aug 29 12:20:21 AM UTC 24 13056465 ps
T726 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.1532568455 Aug 29 12:20:09 AM UTC 24 Aug 29 12:20:22 AM UTC 24 266530144 ps
T727 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.1749455007 Aug 29 12:20:10 AM UTC 24 Aug 29 12:20:25 AM UTC 24 5011036528 ps
T728 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.1687633639 Aug 29 12:20:20 AM UTC 24 Aug 29 12:20:25 AM UTC 24 72523371 ps
T729 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.3327066993 Aug 29 12:20:15 AM UTC 24 Aug 29 12:20:26 AM UTC 24 165664925 ps
T730 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.345741830 Aug 29 12:20:07 AM UTC 24 Aug 29 12:20:27 AM UTC 24 629118291 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3722258139 Aug 29 12:19:44 AM UTC 24 Aug 29 12:20:28 AM UTC 24 1451026013 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.843866596 Aug 29 12:20:26 AM UTC 24 Aug 29 12:20:29 AM UTC 24 25926719 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.3585329709 Aug 29 12:20:26 AM UTC 24 Aug 29 12:20:29 AM UTC 24 17176338 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.1167481871 Aug 29 12:20:22 AM UTC 24 Aug 29 12:20:30 AM UTC 24 892420212 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.631024420 Aug 29 12:20:28 AM UTC 24 Aug 29 12:20:30 AM UTC 24 21773652 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.696032622 Aug 29 12:20:08 AM UTC 24 Aug 29 12:20:31 AM UTC 24 524461457 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.534286340 Aug 29 12:21:10 AM UTC 24 Aug 29 12:21:15 AM UTC 24 53733326 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.300710440 Aug 29 12:20:20 AM UTC 24 Aug 29 12:20:31 AM UTC 24 742089404 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.2094441100 Aug 29 12:18:05 AM UTC 24 Aug 29 12:20:31 AM UTC 24 4256278100 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.103491448 Aug 29 12:20:16 AM UTC 24 Aug 29 12:20:32 AM UTC 24 312246916 ps
T731 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.3147616789 Aug 29 12:20:16 AM UTC 24 Aug 29 12:20:33 AM UTC 24 385220766 ps
T732 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.510297698 Aug 29 12:20:23 AM UTC 24 Aug 29 12:20:33 AM UTC 24 269529358 ps
T733 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.26018936 Aug 29 12:20:22 AM UTC 24 Aug 29 12:20:33 AM UTC 24 2746663734 ps
T734 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.1745131558 Aug 29 12:20:15 AM UTC 24 Aug 29 12:20:34 AM UTC 24 2037905968 ps
T735 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2206314608 Aug 29 12:20:30 AM UTC 24 Aug 29 12:20:36 AM UTC 24 82173344 ps
T736 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.938056679 Aug 29 12:20:00 AM UTC 24 Aug 29 12:20:36 AM UTC 24 358514164 ps
T737 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3533664550 Aug 29 12:20:16 AM UTC 24 Aug 29 12:20:36 AM UTC 24 3916394188 ps
T738 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.585784513 Aug 29 12:20:34 AM UTC 24 Aug 29 12:20:37 AM UTC 24 244398539 ps
T739 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.2579556952 Aug 29 12:20:08 AM UTC 24 Aug 29 12:20:38 AM UTC 24 4978053500 ps
T740 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1197141892 Aug 29 12:20:36 AM UTC 24 Aug 29 12:20:38 AM UTC 24 35097173 ps
T741 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.1577161357 Aug 29 12:20:15 AM UTC 24 Aug 29 12:20:38 AM UTC 24 3815899667 ps
T742 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.4043337949 Aug 29 12:20:31 AM UTC 24 Aug 29 12:20:39 AM UTC 24 1178189124 ps
T743 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.2105276688 Aug 29 12:20:24 AM UTC 24 Aug 29 12:20:40 AM UTC 24 1562396432 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.3166226953 Aug 29 12:20:34 AM UTC 24 Aug 29 12:20:41 AM UTC 24 119065992 ps
T744 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.3888141736 Aug 29 12:20:37 AM UTC 24 Aug 29 12:20:41 AM UTC 24 137776005 ps
T745 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.3038022377 Aug 29 12:20:30 AM UTC 24 Aug 29 12:20:41 AM UTC 24 395581875 ps
T746 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.1886410732 Aug 29 12:20:37 AM UTC 24 Aug 29 12:20:41 AM UTC 24 68143338 ps
T747 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.3489782203 Aug 29 12:20:20 AM UTC 24 Aug 29 12:20:42 AM UTC 24 588480649 ps
T748 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.3490652432 Aug 29 12:20:23 AM UTC 24 Aug 29 12:20:42 AM UTC 24 1587393625 ps
T749 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.3853416531 Aug 29 12:20:13 AM UTC 24 Aug 29 12:20:44 AM UTC 24 771008986 ps
T750 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.685636886 Aug 29 12:20:39 AM UTC 24 Aug 29 12:20:44 AM UTC 24 87960255 ps
T751 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.3424202279 Aug 29 12:20:42 AM UTC 24 Aug 29 12:20:45 AM UTC 24 18035676 ps
T752 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.440510187 Aug 29 12:20:42 AM UTC 24 Aug 29 12:20:45 AM UTC 24 32951560 ps
T753 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.2284961692 Aug 29 12:20:33 AM UTC 24 Aug 29 12:20:46 AM UTC 24 4355100836 ps
T754 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.176440098 Aug 29 12:20:20 AM UTC 24 Aug 29 12:20:46 AM UTC 24 334301927 ps
T755 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.3252077725 Aug 29 12:20:42 AM UTC 24 Aug 29 12:20:47 AM UTC 24 60959063 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.1647443044 Aug 29 12:17:23 AM UTC 24 Aug 29 12:20:47 AM UTC 24 7545445065 ps
T756 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.1082975192 Aug 29 12:20:31 AM UTC 24 Aug 29 12:20:48 AM UTC 24 2839295108 ps
T757 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.1027799337 Aug 29 12:20:45 AM UTC 24 Aug 29 12:20:49 AM UTC 24 52481194 ps
T758 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.1767938006 Aug 29 12:20:44 AM UTC 24 Aug 29 12:20:50 AM UTC 24 374923487 ps
T759 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.3534804635 Aug 29 12:20:33 AM UTC 24 Aug 29 12:20:52 AM UTC 24 321441975 ps
T760 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3577849514 Aug 29 12:20:50 AM UTC 24 Aug 29 12:20:52 AM UTC 24 34795846 ps
T761 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.3887243345 Aug 29 12:20:39 AM UTC 24 Aug 29 12:20:53 AM UTC 24 510203112 ps
T762 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.4260756757 Aug 29 12:20:40 AM UTC 24 Aug 29 12:20:54 AM UTC 24 639751618 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3269801634 Aug 29 12:20:52 AM UTC 24 Aug 29 12:20:55 AM UTC 24 41729824 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.1263669391 Aug 29 12:20:46 AM UTC 24 Aug 29 12:20:55 AM UTC 24 747958153 ps
T765 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.780335129 Aug 29 12:20:51 AM UTC 24 Aug 29 12:20:55 AM UTC 24 120549040 ps
T766 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.3760625117 Aug 29 12:20:33 AM UTC 24 Aug 29 12:20:55 AM UTC 24 652548973 ps
T767 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.1024591201 Aug 29 12:20:30 AM UTC 24 Aug 29 12:20:56 AM UTC 24 1460509067 ps
T768 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.1369569031 Aug 29 12:20:37 AM UTC 24 Aug 29 12:20:56 AM UTC 24 2982081548 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.188301859 Aug 29 12:20:29 AM UTC 24 Aug 29 12:20:58 AM UTC 24 364722763 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.3915107320 Aug 29 12:20:41 AM UTC 24 Aug 29 12:20:58 AM UTC 24 327730456 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.1135396427 Aug 29 12:20:55 AM UTC 24 Aug 29 12:20:58 AM UTC 24 63374404 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.3224479533 Aug 29 12:20:46 AM UTC 24 Aug 29 12:20:59 AM UTC 24 411285432 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.4194431759 Aug 29 12:18:52 AM UTC 24 Aug 29 12:21:00 AM UTC 24 24898063448 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.1404184291 Aug 29 12:20:10 AM UTC 24 Aug 29 12:21:00 AM UTC 24 8663854796 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.3005830489 Aug 29 12:20:37 AM UTC 24 Aug 29 12:21:01 AM UTC 24 346601509 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.2424675040 Aug 29 12:20:47 AM UTC 24 Aug 29 12:21:01 AM UTC 24 329229178 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.3955692507 Aug 29 12:20:55 AM UTC 24 Aug 29 12:21:02 AM UTC 24 158410410 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.316046641 Aug 29 12:21:00 AM UTC 24 Aug 29 12:21:02 AM UTC 24 40790456 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.2470234315 Aug 29 12:20:36 AM UTC 24 Aug 29 12:21:03 AM UTC 24 454494798 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2229917038 Aug 29 12:21:01 AM UTC 24 Aug 29 12:21:04 AM UTC 24 13577074 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.1325329177 Aug 29 12:20:47 AM UTC 24 Aug 29 12:21:04 AM UTC 24 349913142 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.1519842700 Aug 29 12:20:56 AM UTC 24 Aug 29 12:21:04 AM UTC 24 394806107 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.2157499581 Aug 29 12:20:56 AM UTC 24 Aug 29 12:21:05 AM UTC 24 1110426241 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.163648015 Aug 29 12:21:01 AM UTC 24 Aug 29 12:21:05 AM UTC 24 87602795 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.3263082232 Aug 29 12:21:03 AM UTC 24 Aug 29 12:21:07 AM UTC 24 94246869 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.3879845374 Aug 29 12:20:42 AM UTC 24 Aug 29 12:21:09 AM UTC 24 725436637 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.288298839 Aug 29 12:20:49 AM UTC 24 Aug 29 12:21:10 AM UTC 24 1467301270 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.3134708633 Aug 29 12:20:56 AM UTC 24 Aug 29 12:21:14 AM UTC 24 313219722 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.4004114149 Aug 29 12:21:07 AM UTC 24 Aug 29 12:21:11 AM UTC 24 187932786 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.272278566 Aug 29 12:21:12 AM UTC 24 Aug 29 12:21:15 AM UTC 24 82824836 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.12310127 Aug 29 12:21:01 AM UTC 24 Aug 29 12:21:11 AM UTC 24 89127993 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.964035062 Aug 29 12:20:57 AM UTC 24 Aug 29 12:21:12 AM UTC 24 1000909951 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1052654766 Aug 29 12:21:11 AM UTC 24 Aug 29 12:21:14 AM UTC 24 25457263 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.892551835 Aug 29 12:21:05 AM UTC 24 Aug 29 12:21:15 AM UTC 24 430855200 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.1839926748 Aug 29 12:21:04 AM UTC 24 Aug 29 12:21:16 AM UTC 24 354672770 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.2244657998 Aug 29 12:20:45 AM UTC 24 Aug 29 12:21:16 AM UTC 24 706083373 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.4203702150 Aug 29 12:20:57 AM UTC 24 Aug 29 12:21:17 AM UTC 24 406485351 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.2981310069 Aug 29 12:21:05 AM UTC 24 Aug 29 12:21:19 AM UTC 24 484982733 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.1598564059 Aug 29 12:21:17 AM UTC 24 Aug 29 12:21:20 AM UTC 24 16770552 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.4122780942 Aug 29 12:21:14 AM UTC 24 Aug 29 12:21:20 AM UTC 24 130320112 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3248111219 Aug 29 12:21:18 AM UTC 24 Aug 29 12:21:20 AM UTC 24 10713357 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.3764556605 Aug 29 12:21:05 AM UTC 24 Aug 29 12:21:21 AM UTC 24 4655994022 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.375730513 Aug 29 12:21:18 AM UTC 24 Aug 29 12:21:21 AM UTC 24 62670633 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.1089581598 Aug 29 12:21:12 AM UTC 24 Aug 29 12:21:22 AM UTC 24 254481192 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.2559961001 Aug 29 12:21:03 AM UTC 24 Aug 29 12:21:23 AM UTC 24 399975529 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3001781771 Aug 29 12:19:13 AM UTC 24 Aug 29 12:21:24 AM UTC 24 5687547459 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2130933833 Aug 29 12:14:01 AM UTC 24 Aug 29 12:21:26 AM UTC 24 54338340406 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.86758413 Aug 29 12:21:22 AM UTC 24 Aug 29 12:21:26 AM UTC 24 304618965 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.1308859645 Aug 29 12:20:53 AM UTC 24 Aug 29 12:21:27 AM UTC 24 812359525 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.3397879749 Aug 29 12:21:28 AM UTC 24 Aug 29 12:21:31 AM UTC 24 22740869 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.2252971476 Aug 29 12:21:13 AM UTC 24 Aug 29 12:21:32 AM UTC 24 501989155 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.376687482 Aug 29 12:21:12 AM UTC 24 Aug 29 12:21:32 AM UTC 24 464608633 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.4118297845 Aug 29 12:20:17 AM UTC 24 Aug 29 12:21:32 AM UTC 24 36480735586 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.1866290220 Aug 29 12:21:04 AM UTC 24 Aug 29 12:21:32 AM UTC 24 882971885 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1068002914 Aug 29 12:21:17 AM UTC 24 Aug 29 12:21:33 AM UTC 24 3161104119 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1781195524 Aug 29 12:19:21 AM UTC 24 Aug 29 12:21:33 AM UTC 24 2273265266 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.1040252483 Aug 29 12:21:22 AM UTC 24 Aug 29 12:21:33 AM UTC 24 542838562 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3043470795 Aug 29 12:21:17 AM UTC 24 Aug 29 12:21:34 AM UTC 24 328362894 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3363891607 Aug 29 12:19:38 AM UTC 24 Aug 29 12:21:34 AM UTC 24 4486714495 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.938535843 Aug 29 12:21:01 AM UTC 24 Aug 29 12:21:34 AM UTC 24 574180970 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.572982524 Aug 29 12:21:21 AM UTC 24 Aug 29 12:21:34 AM UTC 24 67760180 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.275214116 Aug 29 12:21:31 AM UTC 24 Aug 29 12:21:35 AM UTC 24 121709971 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.3875474337 Aug 29 12:21:22 AM UTC 24 Aug 29 12:21:35 AM UTC 24 4924257039 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3330599006 Aug 29 12:21:33 AM UTC 24 Aug 29 12:21:35 AM UTC 24 15879593 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.2057824094 Aug 29 12:21:14 AM UTC 24 Aug 29 12:21:35 AM UTC 24 1649805966 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.703790796 Aug 29 12:21:33 AM UTC 24 Aug 29 12:21:39 AM UTC 24 295767831 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.751373831 Aug 29 12:21:37 AM UTC 24 Aug 29 12:21:39 AM UTC 24 24989991 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.1394777292 Aug 29 12:21:36 AM UTC 24 Aug 29 12:21:39 AM UTC 24 34401889 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.3541309931 Aug 29 12:21:24 AM UTC 24 Aug 29 12:21:39 AM UTC 24 328692471 ps
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