Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58139039

1

T1

947

T2

718

T3

1552

auto[1]

1125499

1

T4

198

T5

196

T14

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58132269

1

T1

947

T2

718

T3

1552

auto[1]

1132269

1

T4

297

T5

294

T14

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5512577	1			T1	89		T2	109		T3	227
auto[IdleSt]	16166697	1			T1	16		T2	1		T3	540
auto[ClkMuxSt]	29151	1			T1	1		T3	3		T4	5
auto[CntIncrSt]	28985	1			T1	1		T3	3		T4	5
auto[CntProgSt]	1114285	1			T1	15		T3	57		T4	10
auto[TransCheckSt]	22938	1			T1	1		T3	3		T13	1
auto[TokenHashSt]	14701251	1			T1	21		T3	32		T13	192
auto[FlashRmaSt]	27347	1			T3	3		T6	63		T14	34
auto[TokenCheck0St]	10082	1			T3	3		T6	12		T14	7
auto[TokenCheck1St]	7202	1			T3	3		T6	12		T14	7
auto[TransProgSt]	237365	1			T3	81		T6	193		T14	2442
auto[PostTransSt]	8694308	1			T1	803		T3	597		T4	271
auto[ScrapSt]	113694	1			T2	608		T6	315		T21	12
auto[EscalateSt]	4765712	1			T4	607		T5	2053		T14	1213
auto[InvalidSt]	7831607	1			T14	710		T23	493		T46	577

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1337	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7831607	1			T14	710		T23	493		T46	577
EscalateSt	4765712	1			T4	607		T5	2053		T14	1213
ScrapSt	113694	1			T2	608		T6	315		T21	12
PostTransSt	8694308	1			T1	803		T3	597		T4	271
TransProgSt	237365	1			T3	81		T6	193		T14	2442
TokenCheck1St	7202	1			T3	3		T6	12		T14	7
TokenCheck0St	10082	1			T3	3		T6	12		T14	7
FlashRmaSt	27347	1			T3	3		T6	63		T14	34
TokenHashSt	14701251	1			T1	21		T3	32		T13	192
TransCheckSt	22938	1			T1	1		T3	3		T13	1
CntProgSt	1114285	1			T1	15		T3	57		T4	10
CntIncrSt	28985	1			T1	1		T3	3		T4	5
ClkMuxSt	29151	1			T1	1		T3	3		T4	5
IdleSt	16166697	1			T1	16		T2	1		T3	540
ResetSt	5512577	1			T1	89		T2	109		T3	227
arcs[ResetSt=>IdleSt]	42685	1			T1	1		T2	1		T3	3
arcs[IdleSt=>ScrapSt]	226	1			T2	1		T6	1		T21	3
arcs[IdleSt=>ClkMuxSt]	29022	1			T1	1		T3	3		T4	5
arcs[ClkMuxSt=>CntIncrSt]	28985	1			T1	1		T3	3		T4	5
arcs[CntIncrSt=>PostTransSt]	1317	1			T22	11		T24	13		T25	5
arcs[CntIncrSt=>CntProgSt]	27597	1			T1	1		T3	3		T4	5
arcs[CntProgSt=>PostTransSt]	3579	1			T4	5		T5	5		T19	4
arcs[CntProgSt=>TransCheckSt]	22938	1			T1	1		T3	3		T13	1
arcs[TransCheckSt=>PostTransSt]	3236	1			T22	6		T26	38		T24	5
arcs[TransCheckSt=>TokenHashSt]	19595	1			T1	1		T3	3		T13	1
arcs[TokenHashSt=>PostTransSt]	8712	1			T1	1		T13	1		T22	30
arcs[TokenHashSt=>FlashRmaSt]	10120	1			T3	3		T6	12		T14	7
arcs[FlashRmaSt=>TokenCheck0St]	10082	1			T3	3		T6	12		T14	7
arcs[TokenCheck0St=>PostTransSt]	2825	1			T22	11		T23	12		T26	32
arcs[TokenCheck0St=>TokenCheck1St]	7202	1			T3	3		T6	12		T14	7
arcs[TokenCheck1St=>PostTransSt]	619	1			T26	13		T28	5		T52	3
arcs[TransProgSt=>PostTransSt]	5746	1			T3	3		T6	12		T14	7
arcs[IdleSt=>EscalateSt]	146	1			T21	7		T58	8		T59	7
arcs[ClkMuxSt=>EscalateSt]	37	1			T21	1		T58	2		T59	4
arcs[CntIncrSt=>EscalateSt]	71	1			T21	2		T60	1		T59	4
arcs[CntProgSt=>EscalateSt]	1080	1			T21	18		T27	38		T60	18
arcs[TransCheckSt=>EscalateSt]	107	1			T21	3		T60	1		T65	1
arcs[TokenHashSt=>EscalateSt]	763	1			T21	16		T27	13		T60	9
arcs[FlashRmaSt=>EscalateSt]	38	1			T21	1		T58	1		T59	1
arcs[TokenCheck0St=>EscalateSt]	55	1			T27	1		T60	2		T58	1
arcs[TokenCheck1St=>EscalateSt]	26	1			T60	1		T58	1		T64	1
arcs[TransProgSt=>EscalateSt]	811	1			T21	14		T27	25		T60	16
arcs[PostTransSt=>EscalateSt]	3868	1			T4	5		T5	5		T19	4
arcs[InvalidSt=>EscalateSt]	9993	1			T14	5		T23	7		T46	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5512406	1			T1	89		T2	109		T3	227
auto[0]	auto[IdleSt]	16166587	1			T1	16		T2	1		T3	540
auto[0]	auto[ClkMuxSt]	29125	1			T1	1		T3	3		T4	5
auto[0]	auto[CntIncrSt]	28934	1			T1	1		T3	3		T4	5
auto[0]	auto[CntProgSt]	1113563	1			T1	15		T3	57		T4	10
auto[0]	auto[TransCheckSt]	22860	1			T1	1		T3	3		T13	1
auto[0]	auto[TokenHashSt]	14700744	1			T1	21		T3	32		T13	192
auto[0]	auto[FlashRmaSt]	27326	1			T3	3		T6	63		T14	34
auto[0]	auto[TokenCheck0St]	10046	1			T3	3		T6	12		T14	7
auto[0]	auto[TokenCheck1St]	7182	1			T3	3		T6	12		T14	7
auto[0]	auto[TransProgSt]	236835	1			T3	81		T6	193		T14	2442
auto[0]	auto[PostTransSt]	8692355	1			T1	803		T3	597		T4	269
auto[0]	auto[ScrapSt]	113657	1			T2	608		T6	315		T21	9
auto[0]	auto[EscalateSt]	3649449	1			T4	411		T5	1859		T14	919
auto[0]	auto[InvalidSt]	7826633	1			T14	707		T23	489		T46	574
auto[1]	auto[ResetSt]	171	1			T21	4		T27	3		T60	3
auto[1]	auto[IdleSt]	110	1			T21	5		T58	8		T59	6
auto[1]	auto[ClkMuxSt]	26	1			T58	2		T59	2		T64	2
auto[1]	auto[CntIncrSt]	51	1			T21	1		T59	2		T64	2
auto[1]	auto[CntProgSt]	722	1			T21	11		T27	23		T60	7
auto[1]	auto[TransCheckSt]	78	1			T21	1		T60	1		T65	1
auto[1]	auto[TokenHashSt]	507	1			T21	10		T27	9		T60	7
auto[1]	auto[FlashRmaSt]	21	1			T21	1		T58	1		T59	1
auto[1]	auto[TokenCheck0St]	36	1			T27	1		T60	1		T58	1
auto[1]	auto[TokenCheck1St]	20	1			T64	1		T221	1		T222	1
auto[1]	auto[TransProgSt]	530	1			T21	7		T27	18		T60	12
auto[1]	auto[PostTransSt]	1953	1			T4	2		T5	2		T19	2
auto[1]	auto[ScrapSt]	37	1			T21	3		T65	7		T64	1
auto[1]	auto[EscalateSt]	1116263	1			T4	196		T5	194		T14	294
auto[1]	auto[InvalidSt]	4974	1			T14	3		T23	4		T46	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5512420	1			T1	89		T2	109		T3	227
auto[0]	auto[IdleSt]	16166603	1			T1	16		T2	1		T3	540
auto[0]	auto[ClkMuxSt]	29128	1			T1	1		T3	3		T4	5
auto[0]	auto[CntIncrSt]	28932	1			T1	1		T3	3		T4	5
auto[0]	auto[CntProgSt]	1113569	1			T1	15		T3	57		T4	10
auto[0]	auto[TransCheckSt]	22872	1			T1	1		T3	3		T13	1
auto[0]	auto[TokenHashSt]	14700718	1			T1	21		T3	32		T13	192
auto[0]	auto[FlashRmaSt]	27320	1			T3	3		T6	63		T14	34
auto[0]	auto[TokenCheck0St]	10048	1			T3	3		T6	12		T14	7
auto[0]	auto[TokenCheck1St]	7189	1			T3	3		T6	12		T14	7
auto[0]	auto[TransProgSt]	236822	1			T3	81		T6	193		T14	2442
auto[0]	auto[PostTransSt]	8692302	1			T1	803		T3	597		T4	268
auto[0]	auto[ScrapSt]	113660	1			T2	608		T6	315		T21	12
auto[0]	auto[EscalateSt]	3642761	1			T4	313		T5	1762		T14	1017
auto[0]	auto[InvalidSt]	7826588	1			T14	708		T23	490		T46	576
auto[1]	auto[ResetSt]	157	1			T21	3		T60	1		T58	3
auto[1]	auto[IdleSt]	94	1			T21	5		T58	3		T59	6
auto[1]	auto[ClkMuxSt]	23	1			T21	1		T59	4		T64	2
auto[1]	auto[CntIncrSt]	53	1			T21	2		T60	1		T59	4
auto[1]	auto[CntProgSt]	716	1			T21	12		T27	23		T60	15
auto[1]	auto[TransCheckSt]	66	1			T21	2		T223	6		T188	4
auto[1]	auto[TokenHashSt]	533	1			T21	10		T27	9		T60	5
auto[1]	auto[FlashRmaSt]	27	1			T58	1		T59	1		T65	2
auto[1]	auto[TokenCheck0St]	34	1			T60	2		T224	1		T225	2
auto[1]	auto[TokenCheck1St]	13	1			T60	1		T58	1		T64	1
auto[1]	auto[TransProgSt]	543	1			T21	9		T27	17		T60	9
auto[1]	auto[PostTransSt]	2006	1			T4	3		T5	3		T19	2
auto[1]	auto[ScrapSt]	34	1			T60	1		T59	1		T65	3
auto[1]	auto[EscalateSt]	1122951	1			T4	294		T5	291		T14	196
auto[1]	auto[InvalidSt]	5019	1			T14	2		T23	3		T46	1