Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.30 97.92 95.75 93.40 100.00 98.52 99.25 96.29


Total tests in report: 1007
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
61.56 61.56 79.55 79.55 52.22 52.22 50.10 50.10 40.48 40.48 72.67 72.67 92.29 92.29 43.64 43.64 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.340659744
72.01 10.45 87.06 7.51 79.39 27.17 68.23 18.13 42.86 2.38 83.26 10.59 94.53 2.24 48.76 5.12 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.554612883
79.92 7.91 88.13 1.07 80.31 0.92 76.31 8.08 71.43 28.57 89.19 5.93 94.53 0.00 59.54 10.78 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.195325625
84.36 4.44 95.48 7.36 81.15 0.83 77.54 1.23 78.57 7.14 92.37 3.18 94.53 0.00 70.85 11.31 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.134826047
87.37 3.02 96.19 0.71 85.77 4.62 78.25 0.71 85.71 7.14 94.07 1.69 94.78 0.25 76.86 6.01 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2163741275
89.59 2.21 96.25 0.05 85.95 0.18 84.38 6.13 90.48 4.76 94.70 0.64 94.78 0.00 80.57 3.71 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.775331465
90.88 1.29 96.45 0.20 88.54 2.59 84.42 0.04 90.48 0.00 95.34 0.64 95.77 1.00 85.16 4.59 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.464919470
91.79 0.91 96.55 0.10 88.54 0.00 84.42 0.00 95.24 4.76 95.76 0.42 95.77 0.00 86.22 1.06 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1791533315
92.63 0.84 96.65 0.10 89.28 0.74 84.98 0.56 97.62 2.38 96.40 0.64 96.02 0.25 87.46 1.24 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.3705346388
93.40 0.77 96.65 0.00 89.28 0.00 89.86 4.88 97.62 0.00 96.40 0.00 96.02 0.00 87.99 0.53 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.1520507601
94.10 0.70 97.21 0.56 90.11 0.83 90.04 0.18 97.62 0.00 97.03 0.64 96.77 0.75 89.93 1.94 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.9760415
94.61 0.51 97.26 0.05 91.77 1.66 90.04 0.00 97.62 0.00 97.46 0.42 96.77 0.00 91.34 1.41 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.306184404
95.00 0.39 97.36 0.10 91.87 0.09 90.36 0.32 97.62 0.00 97.88 0.42 96.77 0.00 93.11 1.77 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.3672709637
95.36 0.37 97.36 0.00 91.87 0.00 90.36 0.00 100.00 2.38 97.88 0.00 96.77 0.00 93.29 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.4098450929
95.71 0.35 97.36 0.00 91.87 0.00 92.09 1.72 100.00 0.00 97.88 0.00 96.77 0.00 93.99 0.71 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3884158549
95.92 0.21 97.36 0.00 91.87 0.00 92.09 0.00 100.00 0.00 97.88 0.00 98.26 1.49 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.100985623
96.13 0.21 97.72 0.36 92.79 0.92 92.25 0.16 100.00 0.00 97.88 0.00 98.26 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.101655593
96.29 0.17 97.92 0.20 93.16 0.37 92.25 0.00 100.00 0.00 98.31 0.42 98.26 0.00 94.17 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.4249848315
96.38 0.08 97.92 0.00 93.16 0.00 92.47 0.22 100.00 0.00 98.31 0.00 98.26 0.00 94.52 0.35 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1839347537
96.45 0.07 97.92 0.00 93.16 0.00 92.62 0.15 100.00 0.00 98.31 0.00 98.26 0.00 94.88 0.35 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1432971781
96.51 0.06 97.92 0.00 93.44 0.28 92.62 0.00 100.00 0.00 98.31 0.00 98.26 0.00 95.05 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.336092539
96.57 0.06 97.92 0.00 93.44 0.00 93.05 0.43 100.00 0.00 98.31 0.00 98.26 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1720077502
96.63 0.05 97.92 0.00 93.81 0.37 93.05 0.00 100.00 0.00 98.31 0.00 98.26 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.424842050
96.68 0.05 97.92 0.00 93.81 0.00 93.05 0.00 100.00 0.00 98.31 0.00 98.26 0.00 95.41 0.35 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.2692741304
96.72 0.05 97.92 0.00 93.90 0.09 93.07 0.02 100.00 0.00 98.52 0.21 98.26 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.810209147
96.76 0.04 97.92 0.00 93.90 0.00 93.35 0.28 100.00 0.00 98.52 0.00 98.26 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.841110991
96.80 0.04 97.92 0.00 94.18 0.28 93.35 0.00 100.00 0.00 98.52 0.00 98.26 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2962422013
96.84 0.04 97.92 0.00 94.45 0.28 93.35 0.00 100.00 0.00 98.52 0.00 98.26 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2195474514
96.88 0.04 97.92 0.00 94.73 0.28 93.35 0.00 100.00 0.00 98.52 0.00 98.26 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.3932968750
96.92 0.04 97.92 0.00 94.73 0.00 93.35 0.00 100.00 0.00 98.52 0.00 98.51 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1101599742
96.95 0.04 97.92 0.00 94.73 0.00 93.35 0.00 100.00 0.00 98.52 0.00 98.76 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3744664997
96.99 0.04 97.92 0.00 94.73 0.00 93.35 0.00 100.00 0.00 98.52 0.00 99.00 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2921074745
97.03 0.04 97.92 0.00 94.73 0.00 93.35 0.00 100.00 0.00 98.52 0.00 99.25 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1061274548
97.06 0.03 97.92 0.00 94.73 0.00 93.38 0.03 100.00 0.00 98.52 0.00 99.25 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2845809318
97.08 0.03 97.92 0.00 94.92 0.18 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2258263419
97.11 0.03 97.92 0.00 95.10 0.18 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4209606061
97.13 0.03 97.92 0.00 95.29 0.18 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3169601836
97.16 0.03 97.92 0.00 95.29 0.00 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.1917574022
97.18 0.03 97.92 0.00 95.29 0.00 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.628224238
97.21 0.03 97.92 0.00 95.29 0.00 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.4009839719
97.24 0.03 97.92 0.00 95.29 0.00 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2374235968
97.25 0.01 97.92 0.00 95.38 0.09 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4178290604
97.26 0.01 97.92 0.00 95.47 0.09 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1683838792
97.27 0.01 97.92 0.00 95.56 0.09 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2101415783
97.29 0.01 97.92 0.00 95.66 0.09 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2019896600
97.30 0.01 97.92 0.00 95.75 0.09 93.38 0.00 100.00 0.00 98.52 0.00 99.25 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1102321315
97.30 0.01 97.92 0.00 95.75 0.00 93.40 0.02 100.00 0.00 98.52 0.00 99.25 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.926855338

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1956765821
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2564525140
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1492111316
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.411314630
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3785110723
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.912470547
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.85204714
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3802700381
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3281544015
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2476377818
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2974253164
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2637700555
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1949944804
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3942483456
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3272752175
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2252881161
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1223249294
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2423676104
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.718725491
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1685984906
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.916442060
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3806526529
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4094810625
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.552808729
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1849211529
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2486459237
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2475522519
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2335519349
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3587077964
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1374544884
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.350292031
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1172166430
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1028377563
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4197761518
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.863366937
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3818003037
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3895185805
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1870599698
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2650169568
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3247799219
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.936617642
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3292736179
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/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.730047618
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/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.2016159573
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Total test records in report: 1007
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2845809318 Sep 01 12:29:55 PM UTC 24 Sep 01 12:29:58 PM UTC 24 86073670 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.1917574022 Sep 01 12:29:56 PM UTC 24 Sep 01 12:29:58 PM UTC 24 29994415 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.1580121012 Sep 01 12:29:55 PM UTC 24 Sep 01 12:29:59 PM UTC 24 62142148 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.4279695733 Sep 01 12:29:56 PM UTC 24 Sep 01 12:29:59 PM UTC 24 49078033 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.926855338 Sep 01 12:29:56 PM UTC 24 Sep 01 12:30:01 PM UTC 24 153578098 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.101655593 Sep 01 12:29:59 PM UTC 24 Sep 01 12:30:02 PM UTC 24 34366891 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2898077184 Sep 01 12:29:59 PM UTC 24 Sep 01 12:30:02 PM UTC 24 38603165 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.554612883 Sep 01 12:29:56 PM UTC 24 Sep 01 12:30:04 PM UTC 24 575734501 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.340659744 Sep 01 12:29:55 PM UTC 24 Sep 01 12:30:04 PM UTC 24 127551635 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.2023779424 Sep 01 12:29:59 PM UTC 24 Sep 01 12:30:05 PM UTC 24 162171641 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.4067284087 Sep 01 12:30:02 PM UTC 24 Sep 01 12:30:06 PM UTC 24 48263492 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3152819335 Sep 01 12:29:57 PM UTC 24 Sep 01 12:30:07 PM UTC 24 510672131 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.1447481822 Sep 01 12:30:05 PM UTC 24 Sep 01 12:30:08 PM UTC 24 11888741 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.2082197310 Sep 01 12:29:56 PM UTC 24 Sep 01 12:30:09 PM UTC 24 533374275 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.1677203289 Sep 01 12:29:57 PM UTC 24 Sep 01 12:30:10 PM UTC 24 692072415 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.195325625 Sep 01 12:29:56 PM UTC 24 Sep 01 12:30:11 PM UTC 24 293935279 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1432971781 Sep 01 12:29:56 PM UTC 24 Sep 01 12:30:12 PM UTC 24 1107491146 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.1087229183 Sep 01 12:30:05 PM UTC 24 Sep 01 12:30:13 PM UTC 24 250418430 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.134826047 Sep 01 12:29:57 PM UTC 24 Sep 01 12:30:13 PM UTC 24 855880615 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.2552355202 Sep 01 12:29:57 PM UTC 24 Sep 01 12:30:16 PM UTC 24 2261849335 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.701457921 Sep 01 12:30:03 PM UTC 24 Sep 01 12:30:16 PM UTC 24 960340407 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.3672709637 Sep 01 12:29:57 PM UTC 24 Sep 01 12:30:17 PM UTC 24 2571036988 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3482185798 Sep 01 12:30:00 PM UTC 24 Sep 01 12:30:17 PM UTC 24 65207631 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2335681468 Sep 01 12:30:04 PM UTC 24 Sep 01 12:30:20 PM UTC 24 431908475 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.9760415 Sep 01 12:30:11 PM UTC 24 Sep 01 12:30:20 PM UTC 24 412463285 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1530908572 Sep 01 12:29:56 PM UTC 24 Sep 01 12:30:20 PM UTC 24 459247697 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.268319910 Sep 01 12:30:12 PM UTC 24 Sep 01 12:30:21 PM UTC 24 377319661 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.585041579 Sep 01 12:30:03 PM UTC 24 Sep 01 12:30:22 PM UTC 24 362008989 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.1761042185 Sep 01 12:30:20 PM UTC 24 Sep 01 12:30:23 PM UTC 24 40675161 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.615320388 Sep 01 12:30:21 PM UTC 24 Sep 01 12:30:24 PM UTC 24 12372851 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.2877063807 Sep 01 12:29:55 PM UTC 24 Sep 01 12:30:25 PM UTC 24 223079250 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1242883539 Sep 01 12:30:21 PM UTC 24 Sep 01 12:30:25 PM UTC 24 23264236 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.1903342943 Sep 01 12:30:09 PM UTC 24 Sep 01 12:30:28 PM UTC 24 498864382 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.4004534139 Sep 01 12:30:24 PM UTC 24 Sep 01 12:30:28 PM UTC 24 203485613 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2312690592 Sep 01 12:30:29 PM UTC 24 Sep 01 12:30:31 PM UTC 24 35973331 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3775734180 Sep 01 12:30:17 PM UTC 24 Sep 01 12:30:32 PM UTC 24 443315506 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.3705346388 Sep 01 12:29:58 PM UTC 24 Sep 01 12:30:32 PM UTC 24 136626818 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.47129719 Sep 01 12:30:14 PM UTC 24 Sep 01 12:30:33 PM UTC 24 1906011477 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.2135155417 Sep 01 12:30:26 PM UTC 24 Sep 01 12:30:35 PM UTC 24 337409021 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.3165242989 Sep 01 12:30:00 PM UTC 24 Sep 01 12:30:36 PM UTC 24 2100121537 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2029305590 Sep 01 12:30:23 PM UTC 24 Sep 01 12:30:38 PM UTC 24 70440709 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.4061644114 Sep 01 12:30:29 PM UTC 24 Sep 01 12:30:39 PM UTC 24 938763847 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.533393698 Sep 01 12:30:09 PM UTC 24 Sep 01 12:30:40 PM UTC 24 1821579974 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.1068410184 Sep 01 12:30:26 PM UTC 24 Sep 01 12:30:42 PM UTC 24 354480227 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1894777534 Sep 01 12:30:25 PM UTC 24 Sep 01 12:30:42 PM UTC 24 778599029 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.641070556 Sep 01 12:30:14 PM UTC 24 Sep 01 12:30:46 PM UTC 24 696659793 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.3278054655 Sep 01 12:30:38 PM UTC 24 Sep 01 12:30:48 PM UTC 24 3348115876 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3133809327 Sep 01 12:30:48 PM UTC 24 Sep 01 12:30:51 PM UTC 24 15584985 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2163741275 Sep 01 12:30:18 PM UTC 24 Sep 01 12:30:52 PM UTC 24 15291868233 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.20774076 Sep 01 12:30:18 PM UTC 24 Sep 01 12:30:52 PM UTC 24 229082460 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.801569676 Sep 01 12:30:13 PM UTC 24 Sep 01 12:30:53 PM UTC 24 1725145912 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.529448360 Sep 01 12:30:36 PM UTC 24 Sep 01 12:30:54 PM UTC 24 475933505 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.1598477732 Sep 01 12:29:57 PM UTC 24 Sep 01 12:30:54 PM UTC 24 9502460009 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.109061929 Sep 01 12:29:57 PM UTC 24 Sep 01 12:30:54 PM UTC 24 1439575438 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.901378203 Sep 01 12:30:52 PM UTC 24 Sep 01 12:30:55 PM UTC 24 29659425 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.22797592 Sep 01 12:30:51 PM UTC 24 Sep 01 12:30:55 PM UTC 24 152781916 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.598708635 Sep 01 12:30:07 PM UTC 24 Sep 01 12:30:55 PM UTC 24 7087516104 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.2485168970 Sep 01 12:30:21 PM UTC 24 Sep 01 12:30:55 PM UTC 24 310546524 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.1954970173 Sep 01 12:30:40 PM UTC 24 Sep 01 12:30:55 PM UTC 24 528207080 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.912388994 Sep 01 12:30:34 PM UTC 24 Sep 01 12:30:56 PM UTC 24 973439719 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1666975849 Sep 01 12:30:41 PM UTC 24 Sep 01 12:30:58 PM UTC 24 1011796112 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.628224238 Sep 01 12:30:56 PM UTC 24 Sep 01 12:30:58 PM UTC 24 29172599 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3008823835 Sep 01 12:30:54 PM UTC 24 Sep 01 12:30:59 PM UTC 24 146874155 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.131636422 Sep 01 12:30:42 PM UTC 24 Sep 01 12:31:00 PM UTC 24 788169125 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.211842742 Sep 01 12:30:55 PM UTC 24 Sep 01 12:31:01 PM UTC 24 71634052 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3379712324 Sep 01 12:30:39 PM UTC 24 Sep 01 12:31:01 PM UTC 24 736243397 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3884158549 Sep 01 12:29:56 PM UTC 24 Sep 01 12:31:04 PM UTC 24 1608987597 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1154107614 Sep 01 12:30:55 PM UTC 24 Sep 01 12:31:05 PM UTC 24 278314362 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.997909562 Sep 01 12:31:00 PM UTC 24 Sep 01 12:31:05 PM UTC 24 885208663 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.2931708610 Sep 01 12:30:57 PM UTC 24 Sep 01 12:31:06 PM UTC 24 664436034 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.1354205460 Sep 01 12:30:56 PM UTC 24 Sep 01 12:31:09 PM UTC 24 1008969867 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.537927167 Sep 01 12:30:56 PM UTC 24 Sep 01 12:31:09 PM UTC 24 403265184 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3500844180 Sep 01 12:31:01 PM UTC 24 Sep 01 12:31:10 PM UTC 24 1116345654 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.2894984242 Sep 01 12:31:07 PM UTC 24 Sep 01 12:31:10 PM UTC 24 26680249 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.564567859 Sep 01 12:30:56 PM UTC 24 Sep 01 12:31:11 PM UTC 24 1206727124 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1791533315 Sep 01 12:30:55 PM UTC 24 Sep 01 12:31:11 PM UTC 24 432328155 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.1603774395 Sep 01 12:31:00 PM UTC 24 Sep 01 12:31:12 PM UTC 24 498557769 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3899694123 Sep 01 12:31:10 PM UTC 24 Sep 01 12:31:13 PM UTC 24 40271902 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.2987453616 Sep 01 12:31:10 PM UTC 24 Sep 01 12:31:14 PM UTC 24 105071763 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.900530301 Sep 01 12:30:47 PM UTC 24 Sep 01 12:31:16 PM UTC 24 465111940 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.1966504251 Sep 01 12:31:03 PM UTC 24 Sep 01 12:31:16 PM UTC 24 208557204 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.4009839719 Sep 01 12:31:15 PM UTC 24 Sep 01 12:31:18 PM UTC 24 11287907 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.3528453301 Sep 01 12:31:11 PM UTC 24 Sep 01 12:31:18 PM UTC 24 61261070 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.2266171900 Sep 01 12:31:01 PM UTC 24 Sep 01 12:31:18 PM UTC 24 274181396 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.2423473831 Sep 01 12:30:10 PM UTC 24 Sep 01 12:31:20 PM UTC 24 3670730207 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.2712504673 Sep 01 12:31:16 PM UTC 24 Sep 01 12:31:21 PM UTC 24 488474012 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.2492775971 Sep 01 12:30:33 PM UTC 24 Sep 01 12:31:21 PM UTC 24 4823450906 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.3209108546 Sep 01 12:31:11 PM UTC 24 Sep 01 12:31:21 PM UTC 24 195996581 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1113159967 Sep 01 12:31:22 PM UTC 24 Sep 01 12:31:27 PM UTC 24 351563044 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2622041006 Sep 01 12:30:53 PM UTC 24 Sep 01 12:31:28 PM UTC 24 426781833 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1474824289 Sep 01 12:31:14 PM UTC 24 Sep 01 12:31:29 PM UTC 24 363690125 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.1421860917 Sep 01 12:31:18 PM UTC 24 Sep 01 12:31:31 PM UTC 24 6617294485 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.2850137705 Sep 01 12:31:13 PM UTC 24 Sep 01 12:31:33 PM UTC 24 466525221 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2001110079 Sep 01 12:31:22 PM UTC 24 Sep 01 12:31:33 PM UTC 24 562885997 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3413302039 Sep 01 12:32:29 PM UTC 24 Sep 01 12:32:41 PM UTC 24 703066951 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.3933504159 Sep 01 12:31:13 PM UTC 24 Sep 01 12:31:34 PM UTC 24 5266668488 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.4273358555 Sep 01 12:31:35 PM UTC 24 Sep 01 12:31:37 PM UTC 24 22069377 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.1104686878 Sep 01 12:31:36 PM UTC 24 Sep 01 12:31:39 PM UTC 24 19192987 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3513752133 Sep 01 12:30:35 PM UTC 24 Sep 01 12:31:39 PM UTC 24 4295234222 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1479371762 Sep 01 12:29:58 PM UTC 24 Sep 01 12:31:39 PM UTC 24 8963818558 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.3978958903 Sep 01 12:31:22 PM UTC 24 Sep 01 12:31:39 PM UTC 24 1666723723 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1989211297 Sep 01 12:31:38 PM UTC 24 Sep 01 12:31:40 PM UTC 24 21403454 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.2164196984 Sep 01 12:31:28 PM UTC 24 Sep 01 12:31:43 PM UTC 24 272902385 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.2451880474 Sep 01 12:31:18 PM UTC 24 Sep 01 12:31:44 PM UTC 24 599531023 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.1520507601 Sep 01 12:30:17 PM UTC 24 Sep 01 12:31:44 PM UTC 24 2006144390 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.373944663 Sep 01 12:31:41 PM UTC 24 Sep 01 12:31:44 PM UTC 24 94938151 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.4198524161 Sep 01 12:30:59 PM UTC 24 Sep 01 12:31:44 PM UTC 24 1469368538 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.245321207 Sep 01 12:31:10 PM UTC 24 Sep 01 12:31:45 PM UTC 24 586364804 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1590207712 Sep 01 12:31:29 PM UTC 24 Sep 01 12:31:46 PM UTC 24 239157673 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.4275326936 Sep 01 12:31:45 PM UTC 24 Sep 01 12:31:47 PM UTC 24 21886562 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.775331465 Sep 01 12:29:58 PM UTC 24 Sep 01 12:31:49 PM UTC 24 9519778223 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.3294610645 Sep 01 12:31:45 PM UTC 24 Sep 01 12:31:49 PM UTC 24 456382505 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.3183573566 Sep 01 12:31:39 PM UTC 24 Sep 01 12:31:51 PM UTC 24 73798420 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.3783308089 Sep 01 12:31:41 PM UTC 24 Sep 01 12:31:51 PM UTC 24 754868412 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.3956277303 Sep 01 12:31:46 PM UTC 24 Sep 01 12:31:53 PM UTC 24 519468138 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1180777590 Sep 01 12:31:22 PM UTC 24 Sep 01 12:31:53 PM UTC 24 5430851436 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.3608947798 Sep 01 12:31:41 PM UTC 24 Sep 01 12:31:54 PM UTC 24 562422147 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.335962529 Sep 01 12:31:44 PM UTC 24 Sep 01 12:31:55 PM UTC 24 1061671947 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.2989363282 Sep 01 12:31:55 PM UTC 24 Sep 01 12:31:58 PM UTC 24 71642369 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1225748355 Sep 01 12:31:00 PM UTC 24 Sep 01 12:31:59 PM UTC 24 10475240788 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.3410352443 Sep 01 12:32:31 PM UTC 24 Sep 01 12:32:44 PM UTC 24 517469553 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2247887749 Sep 01 12:31:56 PM UTC 24 Sep 01 12:32:01 PM UTC 24 185458599 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.326604545 Sep 01 12:31:52 PM UTC 24 Sep 01 12:32:02 PM UTC 24 368432942 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.932928412 Sep 01 12:31:50 PM UTC 24 Sep 01 12:32:05 PM UTC 24 1152204965 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.397315015 Sep 01 12:31:06 PM UTC 24 Sep 01 12:32:05 PM UTC 24 225556360 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.314278445 Sep 01 12:32:35 PM UTC 24 Sep 01 12:32:43 PM UTC 24 245754015 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.4249848315 Sep 01 12:31:20 PM UTC 24 Sep 01 12:32:06 PM UTC 24 1494426371 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.730638289 Sep 01 12:32:02 PM UTC 24 Sep 01 12:32:07 PM UTC 24 86771303 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.2727298469 Sep 01 12:31:52 PM UTC 24 Sep 01 12:32:07 PM UTC 24 1057156346 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.44844250 Sep 01 12:31:46 PM UTC 24 Sep 01 12:32:07 PM UTC 24 4084830354 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.3338968512 Sep 01 12:32:07 PM UTC 24 Sep 01 12:32:09 PM UTC 24 30661944 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.2351340885 Sep 01 12:31:47 PM UTC 24 Sep 01 12:32:09 PM UTC 24 1318083808 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.3072412534 Sep 01 12:31:35 PM UTC 24 Sep 01 12:32:11 PM UTC 24 677244906 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.197182168 Sep 01 12:32:02 PM UTC 24 Sep 01 12:32:14 PM UTC 24 121061915 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.3204027382 Sep 01 12:32:10 PM UTC 24 Sep 01 12:32:16 PM UTC 24 713837992 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.980462871 Sep 01 12:31:39 PM UTC 24 Sep 01 12:32:18 PM UTC 24 2178164290 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3232988648 Sep 01 12:30:56 PM UTC 24 Sep 01 12:32:20 PM UTC 24 5298153669 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.727127564 Sep 01 12:32:04 PM UTC 24 Sep 01 12:32:21 PM UTC 24 493541799 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.1777881919 Sep 01 12:32:03 PM UTC 24 Sep 01 12:32:21 PM UTC 24 1419099869 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.4277030209 Sep 01 12:32:22 PM UTC 24 Sep 01 12:32:25 PM UTC 24 21995417 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2380967577 Sep 01 12:31:50 PM UTC 24 Sep 01 12:32:25 PM UTC 24 1645183306 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1572020245 Sep 01 12:30:43 PM UTC 24 Sep 01 12:32:27 PM UTC 24 12339156089 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1663404571 Sep 01 12:32:05 PM UTC 24 Sep 01 12:32:28 PM UTC 24 411053214 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3841628174 Sep 01 12:32:26 PM UTC 24 Sep 01 12:32:29 PM UTC 24 26480909 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2809959024 Sep 01 12:31:17 PM UTC 24 Sep 01 12:32:29 PM UTC 24 5776940443 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.2588120097 Sep 01 12:32:25 PM UTC 24 Sep 01 12:32:30 PM UTC 24 195684200 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.4202142737 Sep 01 12:32:16 PM UTC 24 Sep 01 12:32:31 PM UTC 24 2277364614 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.1598337384 Sep 01 12:32:08 PM UTC 24 Sep 01 12:32:31 PM UTC 24 1398384504 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.227132410 Sep 01 12:32:20 PM UTC 24 Sep 01 12:32:32 PM UTC 24 396872383 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.293497153 Sep 01 12:32:08 PM UTC 24 Sep 01 12:32:32 PM UTC 24 2287602113 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.2946836387 Sep 01 12:32:07 PM UTC 24 Sep 01 12:32:33 PM UTC 24 680530100 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.3582037709 Sep 01 12:32:10 PM UTC 24 Sep 01 12:32:35 PM UTC 24 1634447231 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.730047618 Sep 01 12:32:14 PM UTC 24 Sep 01 12:32:35 PM UTC 24 791798641 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.240556119 Sep 01 12:32:33 PM UTC 24 Sep 01 12:32:35 PM UTC 24 28665957 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.280596807 Sep 01 12:32:30 PM UTC 24 Sep 01 12:32:36 PM UTC 24 167853029 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1720077502 Sep 01 12:30:32 PM UTC 24 Sep 01 12:32:39 PM UTC 24 13131960907 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2554342403 Sep 01 12:31:45 PM UTC 24 Sep 01 12:32:40 PM UTC 24 3700779210 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1363306704 Sep 01 12:32:33 PM UTC 24 Sep 01 12:32:41 PM UTC 24 136390871 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.3237048178 Sep 01 12:32:30 PM UTC 24 Sep 01 12:32:45 PM UTC 24 2265662052 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.624538854 Sep 01 12:30:45 PM UTC 24 Sep 01 12:32:42 PM UTC 24 8387708057 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.660441045 Sep 01 12:32:36 PM UTC 24 Sep 01 12:32:46 PM UTC 24 1850677571 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.2618737896 Sep 01 12:32:45 PM UTC 24 Sep 01 12:32:48 PM UTC 24 51169034 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1236705159 Sep 01 12:32:36 PM UTC 24 Sep 01 12:32:48 PM UTC 24 1394542148 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.2877006042 Sep 01 12:32:31 PM UTC 24 Sep 01 12:32:48 PM UTC 24 1215260719 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1726955450 Sep 01 12:32:47 PM UTC 24 Sep 01 12:32:49 PM UTC 24 35145962 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.1635898546 Sep 01 12:32:29 PM UTC 24 Sep 01 12:32:49 PM UTC 24 916114033 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.2160712523 Sep 01 12:32:46 PM UTC 24 Sep 01 12:32:51 PM UTC 24 45871762 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1119560047 Sep 01 12:32:12 PM UTC 24 Sep 01 12:32:54 PM UTC 24 4166633778 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2388385386 Sep 01 12:32:42 PM UTC 24 Sep 01 12:32:55 PM UTC 24 359438293 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2374235968 Sep 01 12:32:52 PM UTC 24 Sep 01 12:32:55 PM UTC 24 10310172 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.841110991 Sep 01 12:32:00 PM UTC 24 Sep 01 12:32:56 PM UTC 24 1405741580 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.2848912883 Sep 01 12:32:50 PM UTC 24 Sep 01 12:32:56 PM UTC 24 63396623 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.4151751653 Sep 01 12:32:50 PM UTC 24 Sep 01 12:32:56 PM UTC 24 68641032 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.1697210663 Sep 01 12:32:34 PM UTC 24 Sep 01 12:32:57 PM UTC 24 788054911 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.2325653449 Sep 01 12:32:50 PM UTC 24 Sep 01 12:32:58 PM UTC 24 185734410 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.1201132394 Sep 01 12:32:42 PM UTC 24 Sep 01 12:33:00 PM UTC 24 1141365425 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3150576423 Sep 01 12:32:57 PM UTC 24 Sep 01 12:33:02 PM UTC 24 344628500 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3918551436 Sep 01 12:31:46 PM UTC 24 Sep 01 12:33:02 PM UTC 24 8965939553 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1138484012 Sep 01 12:32:42 PM UTC 24 Sep 01 12:33:03 PM UTC 24 5264186584 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.2246597573 Sep 01 12:32:58 PM UTC 24 Sep 01 12:33:03 PM UTC 24 126492382 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.4268413525 Sep 01 12:31:47 PM UTC 24 Sep 01 12:33:03 PM UTC 24 6256024080 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.3478947671 Sep 01 12:32:55 PM UTC 24 Sep 01 12:33:04 PM UTC 24 2633272497 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2159048232 Sep 01 12:32:40 PM UTC 24 Sep 01 12:33:04 PM UTC 24 4667945200 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.3231242714 Sep 01 12:32:09 PM UTC 24 Sep 01 12:33:04 PM UTC 24 3510819124 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.4005715648 Sep 01 12:32:57 PM UTC 24 Sep 01 12:33:05 PM UTC 24 2556000096 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.927910626 Sep 01 12:32:51 PM UTC 24 Sep 01 12:33:07 PM UTC 24 636998714 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1926208302 Sep 01 12:33:04 PM UTC 24 Sep 01 12:33:07 PM UTC 24 45913594 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1946503960 Sep 01 12:33:05 PM UTC 24 Sep 01 12:33:08 PM UTC 24 30064118 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.764588860 Sep 01 12:32:56 PM UTC 24 Sep 01 12:33:08 PM UTC 24 1742000933 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.3738262183 Sep 01 12:32:50 PM UTC 24 Sep 01 12:33:09 PM UTC 24 847431791 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.3131752692 Sep 01 12:33:04 PM UTC 24 Sep 01 12:33:09 PM UTC 24 100709418 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.2016159573 Sep 01 12:33:01 PM UTC 24 Sep 01 12:33:11 PM UTC 24 435616443 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.861500368 Sep 01 12:33:10 PM UTC 24 Sep 01 12:33:12 PM UTC 24 19543293 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.4183258892 Sep 01 12:33:08 PM UTC 24 Sep 01 12:33:13 PM UTC 24 347569404 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.236157142 Sep 01 12:33:03 PM UTC 24 Sep 01 12:33:18 PM UTC 24 336652167 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3387060 Sep 01 12:33:10 PM UTC 24 Sep 01 12:33:19 PM UTC 24 2125286290 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.721260465 Sep 01 12:33:07 PM UTC 24 Sep 01 12:33:20 PM UTC 24 273525801 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.626229835 Sep 01 12:33:03 PM UTC 24 Sep 01 12:33:21 PM UTC 24 480725390 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2892203846 Sep 01 12:33:14 PM UTC 24 Sep 01 12:33:24 PM UTC 24 316493482 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.3204162168 Sep 01 12:33:09 PM UTC 24 Sep 01 12:33:24 PM UTC 24 363886018 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.3628740327 Sep 01 12:33:11 PM UTC 24 Sep 01 12:33:25 PM UTC 24 1651222115 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.645161502 Sep 01 12:32:36 PM UTC 24 Sep 01 12:33:27 PM UTC 24 1732869052 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.4144800493 Sep 01 12:33:08 PM UTC 24 Sep 01 12:33:27 PM UTC 24 3016953623 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.1526961035 Sep 01 12:32:49 PM UTC 24 Sep 01 12:33:28 PM UTC 24 1790399742 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.1618061065 Sep 01 12:33:19 PM UTC 24 Sep 01 12:33:29 PM UTC 24 363531266 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1061274548 Sep 01 12:32:44 PM UTC 24 Sep 01 12:33:29 PM UTC 24 5087615393 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.2912403336 Sep 01 12:33:09 PM UTC 24 Sep 01 12:33:29 PM UTC 24 1041950886 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3478278399 Sep 01 12:33:28 PM UTC 24 Sep 01 12:33:31 PM UTC 24 45673978 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2307730936 Sep 01 12:33:29 PM UTC 24 Sep 01 12:33:32 PM UTC 24 43286087 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.990694262 Sep 01 12:33:28 PM UTC 24 Sep 01 12:33:32 PM UTC 24 95823545 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1334364434 Sep 01 12:32:07 PM UTC 24 Sep 01 12:33:32 PM UTC 24 14010749782 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.113285564 Sep 01 12:33:06 PM UTC 24 Sep 01 12:33:36 PM UTC 24 163653198 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1421888816 Sep 01 12:32:59 PM UTC 24 Sep 01 12:33:36 PM UTC 24 923858584 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.2380137944 Sep 01 12:33:22 PM UTC 24 Sep 01 12:33:36 PM UTC 24 1824146259 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.305824767 Sep 01 12:33:39 PM UTC 24 Sep 01 12:33:55 PM UTC 24 4954695793 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.233352398 Sep 01 12:33:31 PM UTC 24 Sep 01 12:33:37 PM UTC 24 66632762 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.897481059 Sep 01 12:32:56 PM UTC 24 Sep 01 12:33:37 PM UTC 24 2171115806 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1741975744 Sep 01 12:33:22 PM UTC 24 Sep 01 12:33:38 PM UTC 24 287170597 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3491963868 Sep 01 12:33:20 PM UTC 24 Sep 01 12:33:38 PM UTC 24 4422424847 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.2865536074 Sep 01 12:33:30 PM UTC 24 Sep 01 12:33:38 PM UTC 24 311132300 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3246130980 Sep 01 12:32:57 PM UTC 24 Sep 01 12:33:39 PM UTC 24 45473602439 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2942240616 Sep 01 12:33:24 PM UTC 24 Sep 01 12:33:41 PM UTC 24 344455210 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.3639206007 Sep 01 12:33:37 PM UTC 24 Sep 01 12:33:42 PM UTC 24 158776011 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.186450322 Sep 01 12:33:40 PM UTC 24 Sep 01 12:33:43 PM UTC 24 60069479 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.475357760 Sep 01 12:33:42 PM UTC 24 Sep 01 12:33:44 PM UTC 24 42609861 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3590990563 Sep 01 12:33:33 PM UTC 24 Sep 01 12:33:45 PM UTC 24 2363858573 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.3538609143 Sep 01 12:33:32 PM UTC 24 Sep 01 12:33:45 PM UTC 24 3500436581 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.701993202 Sep 01 12:33:42 PM UTC 24 Sep 01 12:33:45 PM UTC 24 36806748 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.235510043 Sep 01 12:33:33 PM UTC 24 Sep 01 12:33:46 PM UTC 24 1508901997 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.790501416 Sep 01 12:33:45 PM UTC 24 Sep 01 12:33:49 PM UTC 24 230713417 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.2915550890 Sep 01 12:33:36 PM UTC 24 Sep 01 12:33:49 PM UTC 24 788785406 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.4159224412 Sep 01 12:33:04 PM UTC 24 Sep 01 12:33:50 PM UTC 24 5424594600 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.3441760053 Sep 01 12:33:44 PM UTC 24 Sep 01 12:33:51 PM UTC 24 133181745 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1387080952 Sep 01 12:33:39 PM UTC 24 Sep 01 12:33:52 PM UTC 24 549596767 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.1303738562 Sep 01 12:33:39 PM UTC 24 Sep 01 12:33:54 PM UTC 24 361094502 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.3464500599 Sep 01 12:33:39 PM UTC 24 Sep 01 12:33:55 PM UTC 24 413474341 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1168018095 Sep 01 12:33:47 PM UTC 24 Sep 01 12:33:55 PM UTC 24 1066829404 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.2507215376 Sep 01 12:33:50 PM UTC 24 Sep 01 12:33:56 PM UTC 24 150313721 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.386470843 Sep 01 12:33:56 PM UTC 24 Sep 01 12:33:59 PM UTC 24 39501279 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.947897731 Sep 01 12:33:26 PM UTC 24 Sep 01 12:33:59 PM UTC 24 22479824052 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.4098450929 Sep 01 12:33:47 PM UTC 24 Sep 01 12:34:00 PM UTC 24 320159717 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2972965441 Sep 01 12:33:22 PM UTC 24 Sep 01 12:34:02 PM UTC 24 1022502048 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2347917062 Sep 01 12:33:59 PM UTC 24 Sep 01 12:34:02 PM UTC 24 49189499 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.2300889999 Sep 01 12:33:57 PM UTC 24 Sep 01 12:34:04 PM UTC 24 348405270 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.2197914331 Sep 01 12:32:34 PM UTC 24 Sep 01 12:34:04 PM UTC 24 5767743252 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.1950852417 Sep 01 12:33:10 PM UTC 24 Sep 01 12:34:05 PM UTC 24 9922932360 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2146130995 Sep 01 12:34:03 PM UTC 24 Sep 01 12:34:07 PM UTC 24 21814394 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.2954052058 Sep 01 12:33:51 PM UTC 24 Sep 01 12:34:07 PM UTC 24 2127163567 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.943943355 Sep 01 12:33:55 PM UTC 24 Sep 01 12:34:07 PM UTC 24 1368542710 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.992652339 Sep 01 12:35:23 PM UTC 24 Sep 01 12:35:25 PM UTC 24 14101064 ps