Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	874894	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1058233

1

T1

6

T2

1

T3

81

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1647497	1			T1	239		T2	2		T3	91
values[0x0]	142123	1			T1	4		T2	1		T3	25
values[0x1]	143507	1			T1	4		T3	26		T4	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	692965	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1240162

1

T1

85

T2

1

T3

91

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6874	1			T2	1		T4	3		T13	23
valid_sources[0x01]	7459	1			T4	3		T13	7		T14	8
valid_sources[0x02]	6498	1			T4	1		T13	16		T14	5
valid_sources[0x03]	6818	1			T4	5		T13	15		T14	10
valid_sources[0x04]	6917	1			T4	2		T13	10		T14	5
valid_sources[0x05]	5147	1			T4	1		T13	16		T14	4
valid_sources[0x06]	5435	1			T4	4		T13	12		T14	7
valid_sources[0x07]	5522	1			T1	247		T4	2		T13	21
valid_sources[0x08]	8646	1			T4	2		T13	19		T14	3
valid_sources[0x09]	5012	1			T4	1		T13	11		T14	5
valid_sources[0x0a]	4692	1			T4	3		T13	19		T14	4
valid_sources[0x0b]	4937	1			T13	19		T14	5		T16	19
valid_sources[0x0c]	5046	1			T4	2		T13	19		T14	5
valid_sources[0x0d]	5107	1			T4	3		T13	14		T14	3
valid_sources[0x0e]	5119	1			T13	30		T14	8		T16	17
valid_sources[0x0f]	4885	1			T4	1		T13	26		T14	4
valid_sources[0x10]	6086	1			T13	15		T14	7		T16	16
valid_sources[0x11]	8387	1			T13	21		T14	4		T16	17
valid_sources[0x12]	5220	1			T4	2		T13	13		T14	1
valid_sources[0x13]	5937	1			T4	2		T13	17		T14	4
valid_sources[0x14]	4989	1			T4	2		T13	26		T14	5
valid_sources[0x15]	6488	1			T4	1		T13	18		T14	3
valid_sources[0x16]	6947	1			T4	1		T13	21		T14	3
valid_sources[0x17]	7314	1			T13	12		T14	8		T15	1
valid_sources[0x18]	5586	1			T4	1		T13	14		T14	5
valid_sources[0x19]	4919	1			T4	3		T13	26		T14	6
valid_sources[0x1a]	5178	1			T4	1		T13	21		T14	3
valid_sources[0x1b]	8057	1			T4	1		T13	23		T14	5
valid_sources[0x1c]	5062	1			T13	11		T14	2		T16	16
valid_sources[0x1d]	7698	1			T13	24		T14	3		T15	1
valid_sources[0x1e]	6004	1			T13	21		T14	7		T16	9
valid_sources[0x1f]	4877	1			T4	2		T13	18		T14	4
valid_sources[0x20]	8094	1			T4	1		T13	20		T14	7
valid_sources[0x21]	5059	1			T4	2		T13	30		T14	1
valid_sources[0x22]	5289	1			T4	2		T13	15		T14	3
valid_sources[0x23]	5055	1			T4	1		T13	23		T14	2
valid_sources[0x24]	4992	1			T13	27		T14	3		T16	13
valid_sources[0x25]	6205	1			T4	1		T13	22		T14	4
valid_sources[0x26]	4994	1			T4	2		T13	8		T14	6
valid_sources[0x27]	5101	1			T4	2		T13	19		T14	5
valid_sources[0x28]	5274	1			T4	2		T13	17		T14	4
valid_sources[0x29]	5156	1			T4	3		T13	10		T14	4
valid_sources[0x2a]	5086	1			T4	2		T13	11		T14	3
valid_sources[0x2b]	5422	1			T13	18		T14	5		T16	8
valid_sources[0x2c]	5575	1			T4	3		T13	18		T14	4
valid_sources[0x2d]	4957	1			T4	3		T13	9		T14	6
valid_sources[0x2e]	5261	1			T13	15		T14	4		T16	16
valid_sources[0x2f]	5537	1			T13	16		T14	7		T15	2
valid_sources[0x30]	5009	1			T4	4		T13	15		T14	1
valid_sources[0x31]	10628	1			T4	1		T13	18		T14	6
valid_sources[0x32]	6893	1			T4	1		T13	14		T14	6
valid_sources[0x33]	12990	1			T4	2		T13	14		T14	1
valid_sources[0x34]	5159	1			T13	23		T14	12		T16	10
valid_sources[0x35]	5040	1			T4	3		T13	11		T14	9
valid_sources[0x36]	5759	1			T13	19		T14	7		T16	11
valid_sources[0x37]	5523	1			T4	2		T13	19		T14	6
valid_sources[0x38]	4817	1			T4	1		T13	15		T14	7
valid_sources[0x39]	5372	1			T4	1		T13	15		T14	2
valid_sources[0x3a]	5051	1			T13	20		T14	6		T16	16
valid_sources[0x3b]	4957	1			T13	18		T14	8		T16	9
valid_sources[0x3c]	6623	1			T4	3		T13	20		T14	9
valid_sources[0x3d]	6847	1			T4	1		T13	22		T14	4
valid_sources[0x3e]	5248	1			T4	2		T13	25		T14	2
valid_sources[0x3f]	5130	1			T4	2		T13	26		T14	6
valid_sources[0x40]	5263	1			T4	2		T13	26		T14	6
valid_sources[0x41]	6352	1			T13	16		T14	6		T16	20
valid_sources[0x42]	4964	1			T4	1		T13	21		T14	3
valid_sources[0x43]	4835	1			T4	1		T13	20		T14	3
valid_sources[0x44]	4947	1			T4	5		T13	34		T14	3
valid_sources[0x45]	14197	1			T4	2		T13	16		T14	3
valid_sources[0x46]	5322	1			T4	2		T13	19		T14	9
valid_sources[0x47]	6039	1			T4	1		T13	25		T14	12
valid_sources[0x48]	4864	1			T4	1		T13	22		T14	4
valid_sources[0x49]	5373	1			T4	1		T13	28		T14	8
valid_sources[0x4a]	6688	1			T4	2		T13	25		T14	1
valid_sources[0x4b]	5107	1			T4	1		T13	8		T14	7
valid_sources[0x4c]	6271	1			T4	2		T13	17		T14	11
valid_sources[0x4d]	6844	1			T13	16		T14	3		T16	23
valid_sources[0x4e]	5400	1			T4	1		T13	21		T14	4
valid_sources[0x4f]	6685	1			T4	1		T13	17		T14	6
valid_sources[0x50]	13840	1			T4	1		T13	16		T14	5
valid_sources[0x51]	21175	1			T4	2		T13	24		T14	10
valid_sources[0x52]	5023	1			T13	15		T14	2		T16	24
valid_sources[0x53]	5641	1			T4	3		T13	15		T14	13
valid_sources[0x54]	6132	1			T4	1		T13	29		T14	2
valid_sources[0x55]	7163	1			T13	15		T14	10		T15	1
valid_sources[0x56]	5159	1			T4	1		T13	12		T14	5
valid_sources[0x57]	6609	1			T4	1		T13	14		T14	3
valid_sources[0x58]	5800	1			T4	1		T13	21		T14	8
valid_sources[0x59]	9387	1			T4	1		T13	21		T14	1
valid_sources[0x5a]	6290	1			T13	17		T14	10		T16	10
valid_sources[0x5b]	5004	1			T4	1		T13	21		T14	5
valid_sources[0x5c]	5128	1			T13	20		T14	5		T15	1
valid_sources[0x5d]	5050	1			T4	1		T13	12		T14	9
valid_sources[0x5e]	5169	1			T13	15		T14	3		T16	16
valid_sources[0x5f]	5039	1			T2	1		T13	16		T14	5
valid_sources[0x60]	5369	1			T4	1		T13	14		T14	8
valid_sources[0x61]	10849	1			T2	1		T4	2		T13	24
valid_sources[0x62]	5089	1			T4	1		T13	20		T14	5
valid_sources[0x63]	5273	1			T4	1		T13	12		T14	2
valid_sources[0x64]	5202	1			T4	3		T13	23		T14	2
valid_sources[0x65]	5140	1			T4	2		T13	16		T14	3
valid_sources[0x66]	6506	1			T13	16		T14	7		T16	25
valid_sources[0x67]	5552	1			T4	3		T5	407		T13	14
valid_sources[0x68]	4934	1			T13	20		T14	5		T16	18
valid_sources[0x69]	5161	1			T4	1		T13	14		T14	3
valid_sources[0x6a]	5208	1			T13	14		T14	5		T16	23
valid_sources[0x6b]	4958	1			T4	3		T13	16		T14	2
valid_sources[0x6c]	4934	1			T4	1		T13	15		T14	15
valid_sources[0x6d]	6954	1			T4	2		T13	26		T16	18
valid_sources[0x6e]	5318	1			T4	1		T13	27		T14	11
valid_sources[0x6f]	6583	1			T4	3		T13	14		T14	6
valid_sources[0x70]	5390	1			T4	2		T13	26		T14	3
valid_sources[0x71]	5235	1			T4	1		T13	40		T14	6
valid_sources[0x72]	5308	1			T4	2		T13	31		T14	8
valid_sources[0x73]	5180	1			T4	2		T13	19		T14	7
valid_sources[0x74]	6295	1			T4	2		T13	12		T14	4
valid_sources[0x75]	7486	1			T13	9		T14	4		T16	14
valid_sources[0x76]	5652	1			T4	1		T13	25		T14	6
valid_sources[0x77]	5066	1			T4	1		T13	32		T14	4
valid_sources[0x78]	5167	1			T13	17		T14	3		T16	26
valid_sources[0x79]	4807	1			T4	1		T13	15		T14	6
valid_sources[0x7a]	9778	1			T13	20		T14	1		T15	2
valid_sources[0x7b]	4793	1			T13	21		T14	5		T15	1
valid_sources[0x7c]	5129	1			T4	1		T13	22		T14	9
valid_sources[0x7d]	4986	1			T4	5		T13	12		T14	9
valid_sources[0x7e]	5202	1			T4	1		T13	11		T14	7
valid_sources[0x7f]	4895	1			T13	14		T14	4		T16	15
valid_sources[0x80]	4994	1			T13	22		T14	9		T16	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

812389

1

T2

1

T3

35

T4

81

values[0x0]

all_enables

biggest_size

123214

1

T1

2

T3

23

T4

64

values[0x1]

all_enables

biggest_size

122630

1

T1

4

T3

23

T4

54