SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
50.00 | 50.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex | 50.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
50.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 10 | 5 | 5 | 50.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 10 | 5 | 5 | 50.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 10 | 5 | 5 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
others[2] | 0 | 1 | 1 | |
others[5] | 0 | 1 | 1 | |
others[6] | 0 | 1 | 1 | |
others[7] | 0 | 1 | 1 | |
false | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2700 | 1 | T34 | 1 | T6 | 40 | T9 | 32 | ||||
others[1] | 2 | 1 | T231 | 1 | T232 | 1 | - | - | ||||
others[3] | 1 | 1 | T106 | 1 | - | - | - | - | ||||
others[4] | 2 | 1 | T2 | 1 | T47 | 1 | - | - | ||||
true | 40314 | 1 | T1 | 1 | T3 | 7 | T4 | 17 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |