Unified Coverage Report :: Module :: lc_ctrl_reg_top

Module : lc_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.65	100.00	98.61			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.65	100.00	98.61			100.00	100.00
tb.dut.u_reg_tap	99.73	100.00	98.92			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.65	100.00	98.61			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.29	97.79	98.66	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_prog_error	100.00	100.00
u_alert_test_fatal_state_error	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_claim_transition_if	100.00	100.00
u_claim_transition_if_regwen	100.00	100.00	100.00			100.00
u_device_id_0	100.00	100.00
u_device_id_1	100.00	100.00
u_device_id_2	100.00	100.00
u_device_id_3	100.00	100.00
u_device_id_4	100.00	100.00
u_device_id_5	100.00	100.00
u_device_id_6	100.00	100.00
u_device_id_7	100.00	100.00
u_hw_revision0_product_id	33.33	33.33
u_hw_revision0_silicon_creator_id	33.33	33.33
u_hw_revision1_reserved	33.33	33.33
u_hw_revision1_revision_id	33.33	33.33
u_lc_id_state	66.67	66.67
u_lc_state	100.00	100.00
u_lc_transition_cnt	100.00	100.00
u_manuf_state_0	100.00	100.00
u_manuf_state_1	100.00	100.00
u_manuf_state_2	100.00	100.00
u_manuf_state_3	100.00	100.00
u_manuf_state_4	100.00	100.00
u_manuf_state_5	100.00	100.00
u_manuf_state_6	100.00	100.00
u_manuf_state_7	100.00	100.00
u_otp_vendor_test_ctrl	100.00	100.00
u_otp_vendor_test_status	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.97	97.14	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_bus_integ_error	100.00	100.00
u_status_ext_clock_switched	100.00	100.00
u_status_flash_rma_error	100.00	100.00
u_status_initialized	100.00	100.00
u_status_otp_error	100.00	100.00
u_status_otp_partition_error	100.00	100.00
u_status_ready	100.00	100.00
u_status_state_error	100.00	100.00
u_status_token_error	100.00	100.00
u_status_transition_count_error	100.00	100.00
u_status_transition_error	100.00	100.00
u_status_transition_successful	100.00	100.00
u_transition_cmd	100.00	100.00
u_transition_ctrl_ext_clock_en	100.00	100.00
u_transition_ctrl_volatile_raw_unlock	100.00	100.00
u_transition_regwen	100.00	100.00
u_transition_target	100.00	100.00
u_transition_token_0	100.00	100.00
u_transition_token_1	100.00	100.00
u_transition_token_2	100.00	100.00
u_transition_token_3	100.00	100.00

---

Module Instance : tb.dut.u_reg_tap

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.73	100.00	98.92			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.90	97.36	98.54	73.61		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_prog_error	100.00	100.00
u_alert_test_fatal_state_error	100.00	100.00
u_chk	90.18	100.00		70.54			100.00
u_claim_transition_if	100.00	100.00
u_claim_transition_if_regwen	100.00	100.00	100.00			100.00
u_device_id_0	100.00	100.00
u_device_id_1	100.00	100.00
u_device_id_2	100.00	100.00
u_device_id_3	100.00	100.00
u_device_id_4	100.00	100.00
u_device_id_5	100.00	100.00
u_device_id_6	100.00	100.00
u_device_id_7	100.00	100.00
u_hw_revision0_product_id	33.33	33.33
u_hw_revision0_silicon_creator_id	33.33	33.33
u_hw_revision1_reserved	33.33	33.33
u_hw_revision1_revision_id	33.33	33.33
u_lc_id_state	100.00	100.00
u_lc_state	100.00	100.00
u_lc_transition_cnt	100.00	100.00
u_manuf_state_0	100.00	100.00
u_manuf_state_1	100.00	100.00
u_manuf_state_2	100.00	100.00
u_manuf_state_3	100.00	100.00
u_manuf_state_4	100.00	100.00
u_manuf_state_5	100.00	100.00
u_manuf_state_6	100.00	100.00
u_manuf_state_7	100.00	100.00
u_otp_vendor_test_ctrl	100.00	100.00
u_otp_vendor_test_status	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	97.14	92.19	96.36			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_bus_integ_error	100.00	100.00
u_status_ext_clock_switched	100.00	100.00
u_status_flash_rma_error	100.00	100.00
u_status_initialized	100.00	100.00
u_status_otp_error	100.00	100.00
u_status_otp_partition_error	100.00	100.00
u_status_ready	100.00	100.00
u_status_state_error	100.00	100.00
u_status_token_error	100.00	100.00
u_status_transition_count_error	100.00	100.00
u_status_transition_error	100.00	100.00
u_status_transition_successful	100.00	100.00
u_transition_cmd	100.00	100.00
u_transition_ctrl_ext_clock_en	100.00	100.00
u_transition_ctrl_volatile_raw_unlock	100.00	100.00
u_transition_regwen	100.00	100.00
u_transition_target	100.00	100.00
u_transition_token_0	100.00	100.00
u_transition_token_1	100.00	100.00
u_transition_token_2	100.00	100.00
u_transition_token_3	100.00	100.00

Line Coverage for Module : lc_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		227	227	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
CONT_ASSIGN	599	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	671	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	694	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
ALWAYS	1140	36	36	100.00
CONT_ASSIGN	1178	1	1	100.00
ALWAYS	1182	1	1	100.00
CONT_ASSIGN	1221	1	1	100.00
CONT_ASSIGN	1223	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1227	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
CONT_ASSIGN	1231	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1237	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1241	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1251	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1263	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
ALWAYS	1295	36	36	100.00
ALWAYS	1335	53	53	100.00
CONT_ASSIGN	1504	0	0
CONT_ASSIGN	1512	1	1	100.00
CONT_ASSIGN	1513	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : lc_ctrl_reg_top

	Total	Covered	Percent
Conditions	432	426	98.61
Logical	432	426	98.61
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
58-1232	100.00
1233-1291	96.15

---

Branch Coverage for Module : lc_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	1178	2	2	100.00
IF	68	3	3	100.00
CASE	1336	36	36	100.00

1178         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T68,T100,T81
0	0	Covered	T1,T2,T3

1336           unique case (1'b1)
                      -1-  
1337             addr_hit[0]: begin
1338               reg_rdata_next[0] = '0;
                   ==>
1339               reg_rdata_next[1] = '0;
1340               reg_rdata_next[2] = '0;
1341             end
1342       
1343             addr_hit[1]: begin
1344               reg_rdata_next[0] = status_initialized_qs;
                   ==>
1345               reg_rdata_next[1] = status_ready_qs;
1346               reg_rdata_next[2] = status_ext_clock_switched_qs;
1347               reg_rdata_next[3] = status_transition_successful_qs;
1348               reg_rdata_next[4] = status_transition_count_error_qs;
1349               reg_rdata_next[5] = status_transition_error_qs;
1350               reg_rdata_next[6] = status_token_error_qs;
1351               reg_rdata_next[7] = status_flash_rma_error_qs;
1352               reg_rdata_next[8] = status_otp_error_qs;
1353               reg_rdata_next[9] = status_state_error_qs;
1354               reg_rdata_next[10] = status_bus_integ_error_qs;
1355               reg_rdata_next[11] = status_otp_partition_error_qs;
1356             end
1357       
1358             addr_hit[2]: begin
1359               reg_rdata_next[0] = claim_transition_if_regwen_qs;
                   ==>
1360             end
1361       
1362             addr_hit[3]: begin
1363               reg_rdata_next[7:0] = claim_transition_if_qs;
                   ==>
1364             end
1365       
1366             addr_hit[4]: begin
1367               reg_rdata_next[0] = transition_regwen_qs;
                   ==>
1368             end
1369       
1370             addr_hit[5]: begin
1371               reg_rdata_next[0] = '0;
                   ==>
1372             end
1373       
1374             addr_hit[6]: begin
1375               reg_rdata_next[0] = transition_ctrl_ext_clock_en_qs;
                   ==>
1376               reg_rdata_next[1] = transition_ctrl_volatile_raw_unlock_qs;
1377             end
1378       
1379             addr_hit[7]: begin
1380               reg_rdata_next[31:0] = transition_token_0_qs;
                   ==>
1381             end
1382       
1383             addr_hit[8]: begin
1384               reg_rdata_next[31:0] = transition_token_1_qs;
                   ==>
1385             end
1386       
1387             addr_hit[9]: begin
1388               reg_rdata_next[31:0] = transition_token_2_qs;
                   ==>
1389             end
1390       
1391             addr_hit[10]: begin
1392               reg_rdata_next[31:0] = transition_token_3_qs;
                   ==>
1393             end
1394       
1395             addr_hit[11]: begin
1396               reg_rdata_next[29:0] = transition_target_qs;
                   ==>
1397             end
1398       
1399             addr_hit[12]: begin
1400               reg_rdata_next[31:0] = otp_vendor_test_ctrl_qs;
                   ==>
1401             end
1402       
1403             addr_hit[13]: begin
1404               reg_rdata_next[31:0] = otp_vendor_test_status_qs;
                   ==>
1405             end
1406       
1407             addr_hit[14]: begin
1408               reg_rdata_next[29:0] = lc_state_qs;
                   ==>
1409             end
1410       
1411             addr_hit[15]: begin
1412               reg_rdata_next[4:0] = lc_transition_cnt_qs;
                   ==>
1413             end
1414       
1415             addr_hit[16]: begin
1416               reg_rdata_next[31:0] = lc_id_state_qs;
                   ==>
1417             end
1418       
1419             addr_hit[17]: begin
1420               reg_rdata_next[15:0] = hw_revision0_product_id_qs;
                   ==>
1421               reg_rdata_next[31:16] = hw_revision0_silicon_creator_id_qs;
1422             end
1423       
1424             addr_hit[18]: begin
1425               reg_rdata_next[7:0] = hw_revision1_revision_id_qs;
                   ==>
1426               reg_rdata_next[31:8] = hw_revision1_reserved_qs;
1427             end
1428       
1429             addr_hit[19]: begin
1430               reg_rdata_next[31:0] = device_id_0_qs;
                   ==>
1431             end
1432       
1433             addr_hit[20]: begin
1434               reg_rdata_next[31:0] = device_id_1_qs;
                   ==>
1435             end
1436       
1437             addr_hit[21]: begin
1438               reg_rdata_next[31:0] = device_id_2_qs;
                   ==>
1439             end
1440       
1441             addr_hit[22]: begin
1442               reg_rdata_next[31:0] = device_id_3_qs;
                   ==>
1443             end
1444       
1445             addr_hit[23]: begin
1446               reg_rdata_next[31:0] = device_id_4_qs;
                   ==>
1447             end
1448       
1449             addr_hit[24]: begin
1450               reg_rdata_next[31:0] = device_id_5_qs;
                   ==>
1451             end
1452       
1453             addr_hit[25]: begin
1454               reg_rdata_next[31:0] = device_id_6_qs;
                   ==>
1455             end
1456       
1457             addr_hit[26]: begin
1458               reg_rdata_next[31:0] = device_id_7_qs;
                   ==>
1459             end
1460       
1461             addr_hit[27]: begin
1462               reg_rdata_next[31:0] = manuf_state_0_qs;
                   ==>
1463             end
1464       
1465             addr_hit[28]: begin
1466               reg_rdata_next[31:0] = manuf_state_1_qs;
                   ==>
1467             end
1468       
1469             addr_hit[29]: begin
1470               reg_rdata_next[31:0] = manuf_state_2_qs;
                   ==>
1471             end
1472       
1473             addr_hit[30]: begin
1474               reg_rdata_next[31:0] = manuf_state_3_qs;
                   ==>
1475             end
1476       
1477             addr_hit[31]: begin
1478               reg_rdata_next[31:0] = manuf_state_4_qs;
                   ==>
1479             end
1480       
1481             addr_hit[32]: begin
1482               reg_rdata_next[31:0] = manuf_state_5_qs;
                   ==>
1483             end
1484       
1485             addr_hit[33]: begin
1486               reg_rdata_next[31:0] = manuf_state_6_qs;
                   ==>
1487             end
1488       
1489             addr_hit[34]: begin
1490               reg_rdata_next[31:0] = manuf_state_7_qs;
                   ==>
1491             end
1492       
1493             default: begin
1494               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	130715980	2158956	0	0
reAfterRv	130715980	2158956	0	0
rePulse	130715980	1789789	0	0
wePulse	130715980	369167	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	130715980	2158956	0	0
T1	1459	247	0	0
T2	712	3	0	0
T3	2167	142	0	0
T4	8773	336	0	0
T5	5820	407	0	0
T6	20377	96	0	0
T7	18765	119	0	0
T8	22903	143	0	0
T9	0	338	0	0
T10	0	252	0	0
T13	35144	4740	0	0
T14	30973	1343	0	0
T15	2264	52	0	0
T16	42484	3964	0	0
T17	1394	10	0	0
T20	32312	0	0	0
T21	2763	0	0	0
T22	5345	0	0	0
T28	2826	0	0	0
T29	28687	109	0	0
T30	0	247	0	0
T31	0	84	0	0
T32	0	460	0	0
T33	0	584	0	0
T35	1397	0	0	0
T36	1828	0	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	130715980	2158956	0	0
T1	1459	247	0	0
T2	712	3	0	0
T3	2167	142	0	0
T4	8773	336	0	0
T5	5820	407	0	0
T6	20377	96	0	0
T7	18765	119	0	0
T8	22903	143	0	0
T9	0	338	0	0
T10	0	252	0	0
T13	35144	4740	0	0
T14	30973	1343	0	0
T15	2264	52	0	0
T16	42484	3964	0	0
T17	1394	10	0	0
T20	32312	0	0	0
T21	2763	0	0	0
T22	5345	0	0	0
T28	2826	0	0	0
T29	28687	109	0	0
T30	0	247	0	0
T31	0	84	0	0
T32	0	460	0	0
T33	0	584	0	0
T35	1397	0	0	0
T36	1828	0	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	130715980	1789789	0	0
T1	1459	239	0	0
T2	712	2	0	0
T3	2167	91	0	0
T4	8773	200	0	0
T5	5820	215	0	0
T6	20377	49	0	0
T7	18765	48	0	0
T8	22903	79	0	0
T9	0	185	0	0
T10	0	138	0	0
T13	35144	4589	0	0
T14	30973	727	0	0
T15	2264	0	0	0
T16	42484	3508	0	0
T17	1394	2	0	0
T20	32312	0	0	0
T21	2763	0	0	0
T22	5345	0	0	0
T28	2826	0	0	0
T29	28687	61	0	0
T30	0	111	0	0
T31	0	42	0	0
T32	0	375	0	0
T33	0	293	0	0
T34	0	2	0	0
T35	1397	0	0	0
T36	1828	0	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	130715980	369167	0	0
T1	1459	8	0	0
T2	712	1	0	0
T3	2167	51	0	0
T4	8773	136	0	0
T5	5820	192	0	0
T6	20377	47	0	0
T7	18765	71	0	0
T8	22903	64	0	0
T9	0	153	0	0
T10	0	114	0	0
T13	35144	151	0	0
T14	30973	616	0	0
T15	2264	52	0	0
T16	42484	456	0	0
T17	1394	8	0	0
T20	32312	0	0	0
T21	2763	0	0	0
T22	5345	0	0	0
T28	2826	0	0	0
T29	28687	48	0	0
T30	0	136	0	0
T31	0	42	0	0
T32	0	85	0	0
T33	0	291	0	0
T35	1397	0	0	0
T36	1828	0	0	0

Line Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
TOTAL		227	227	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
CONT_ASSIGN	599	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	671	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	694	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
ALWAYS	1140	36	36	100.00
CONT_ASSIGN	1178	1	1	100.00
ALWAYS	1182	1	1	100.00
CONT_ASSIGN	1221	1	1	100.00
CONT_ASSIGN	1223	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1227	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
CONT_ASSIGN	1231	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1237	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1241	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1251	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1263	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
ALWAYS	1295	36	36	100.00
ALWAYS	1335	53	53	100.00
CONT_ASSIGN	1504	0	0
CONT_ASSIGN	1512	1	1	100.00
CONT_ASSIGN	1513	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut.u_reg

	Total	Covered	Percent
Conditions	432	426	98.61
Logical	432	426	98.61
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
58-1232	100.00
1233-1291	96.15

---

Branch Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	1178	2	2	100.00
IF	68	3	3	100.00
CASE	1336	36	36	100.00

1178         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T68,T100,T81
0	0	Covered	T1,T2,T3

1336           unique case (1'b1)
                      -1-  
1337             addr_hit[0]: begin
1338               reg_rdata_next[0] = '0;
                   ==>
1339               reg_rdata_next[1] = '0;
1340               reg_rdata_next[2] = '0;
1341             end
1342       
1343             addr_hit[1]: begin
1344               reg_rdata_next[0] = status_initialized_qs;
                   ==>
1345               reg_rdata_next[1] = status_ready_qs;
1346               reg_rdata_next[2] = status_ext_clock_switched_qs;
1347               reg_rdata_next[3] = status_transition_successful_qs;
1348               reg_rdata_next[4] = status_transition_count_error_qs;
1349               reg_rdata_next[5] = status_transition_error_qs;
1350               reg_rdata_next[6] = status_token_error_qs;
1351               reg_rdata_next[7] = status_flash_rma_error_qs;
1352               reg_rdata_next[8] = status_otp_error_qs;
1353               reg_rdata_next[9] = status_state_error_qs;
1354               reg_rdata_next[10] = status_bus_integ_error_qs;
1355               reg_rdata_next[11] = status_otp_partition_error_qs;
1356             end
1357       
1358             addr_hit[2]: begin
1359               reg_rdata_next[0] = claim_transition_if_regwen_qs;
                   ==>
1360             end
1361       
1362             addr_hit[3]: begin
1363               reg_rdata_next[7:0] = claim_transition_if_qs;
                   ==>
1364             end
1365       
1366             addr_hit[4]: begin
1367               reg_rdata_next[0] = transition_regwen_qs;
                   ==>
1368             end
1369       
1370             addr_hit[5]: begin
1371               reg_rdata_next[0] = '0;
                   ==>
1372             end
1373       
1374             addr_hit[6]: begin
1375               reg_rdata_next[0] = transition_ctrl_ext_clock_en_qs;
                   ==>
1376               reg_rdata_next[1] = transition_ctrl_volatile_raw_unlock_qs;
1377             end
1378       
1379             addr_hit[7]: begin
1380               reg_rdata_next[31:0] = transition_token_0_qs;
                   ==>
1381             end
1382       
1383             addr_hit[8]: begin
1384               reg_rdata_next[31:0] = transition_token_1_qs;
                   ==>
1385             end
1386       
1387             addr_hit[9]: begin
1388               reg_rdata_next[31:0] = transition_token_2_qs;
                   ==>
1389             end
1390       
1391             addr_hit[10]: begin
1392               reg_rdata_next[31:0] = transition_token_3_qs;
                   ==>
1393             end
1394       
1395             addr_hit[11]: begin
1396               reg_rdata_next[29:0] = transition_target_qs;
                   ==>
1397             end
1398       
1399             addr_hit[12]: begin
1400               reg_rdata_next[31:0] = otp_vendor_test_ctrl_qs;
                   ==>
1401             end
1402       
1403             addr_hit[13]: begin
1404               reg_rdata_next[31:0] = otp_vendor_test_status_qs;
                   ==>
1405             end
1406       
1407             addr_hit[14]: begin
1408               reg_rdata_next[29:0] = lc_state_qs;
                   ==>
1409             end
1410       
1411             addr_hit[15]: begin
1412               reg_rdata_next[4:0] = lc_transition_cnt_qs;
                   ==>
1413             end
1414       
1415             addr_hit[16]: begin
1416               reg_rdata_next[31:0] = lc_id_state_qs;
                   ==>
1417             end
1418       
1419             addr_hit[17]: begin
1420               reg_rdata_next[15:0] = hw_revision0_product_id_qs;
                   ==>
1421               reg_rdata_next[31:16] = hw_revision0_silicon_creator_id_qs;
1422             end
1423       
1424             addr_hit[18]: begin
1425               reg_rdata_next[7:0] = hw_revision1_revision_id_qs;
                   ==>
1426               reg_rdata_next[31:8] = hw_revision1_reserved_qs;
1427             end
1428       
1429             addr_hit[19]: begin
1430               reg_rdata_next[31:0] = device_id_0_qs;
                   ==>
1431             end
1432       
1433             addr_hit[20]: begin
1434               reg_rdata_next[31:0] = device_id_1_qs;
                   ==>
1435             end
1436       
1437             addr_hit[21]: begin
1438               reg_rdata_next[31:0] = device_id_2_qs;
                   ==>
1439             end
1440       
1441             addr_hit[22]: begin
1442               reg_rdata_next[31:0] = device_id_3_qs;
                   ==>
1443             end
1444       
1445             addr_hit[23]: begin
1446               reg_rdata_next[31:0] = device_id_4_qs;
                   ==>
1447             end
1448       
1449             addr_hit[24]: begin
1450               reg_rdata_next[31:0] = device_id_5_qs;
                   ==>
1451             end
1452       
1453             addr_hit[25]: begin
1454               reg_rdata_next[31:0] = device_id_6_qs;
                   ==>
1455             end
1456       
1457             addr_hit[26]: begin
1458               reg_rdata_next[31:0] = device_id_7_qs;
                   ==>
1459             end
1460       
1461             addr_hit[27]: begin
1462               reg_rdata_next[31:0] = manuf_state_0_qs;
                   ==>
1463             end
1464       
1465             addr_hit[28]: begin
1466               reg_rdata_next[31:0] = manuf_state_1_qs;
                   ==>
1467             end
1468       
1469             addr_hit[29]: begin
1470               reg_rdata_next[31:0] = manuf_state_2_qs;
                   ==>
1471             end
1472       
1473             addr_hit[30]: begin
1474               reg_rdata_next[31:0] = manuf_state_3_qs;
                   ==>
1475             end
1476       
1477             addr_hit[31]: begin
1478               reg_rdata_next[31:0] = manuf_state_4_qs;
                   ==>
1479             end
1480       
1481             addr_hit[32]: begin
1482               reg_rdata_next[31:0] = manuf_state_5_qs;
                   ==>
1483             end
1484       
1485             addr_hit[33]: begin
1486               reg_rdata_next[31:0] = manuf_state_6_qs;
                   ==>
1487             end
1488       
1489             addr_hit[34]: begin
1490               reg_rdata_next[31:0] = manuf_state_7_qs;
                   ==>
1491             end
1492       
1493             default: begin
1494               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T3,T4
addr_hit[1]	Covered	T1,T3,T4
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T3,T4
addr_hit[6]	Covered	T1,T3,T4
addr_hit[7]	Covered	T1,T3,T4
addr_hit[8]	Covered	T1,T3,T4
addr_hit[9]	Covered	T1,T3,T4
addr_hit[10]	Covered	T1,T3,T4
addr_hit[11]	Covered	T1,T3,T4
addr_hit[12]	Covered	T1,T3,T4
addr_hit[13]	Covered	T1,T3,T4
addr_hit[14]	Covered	T1,T3,T4
addr_hit[15]	Covered	T1,T3,T4
addr_hit[16]	Covered	T1,T3,T4
addr_hit[17]	Covered	T1,T3,T4
addr_hit[18]	Covered	T1,T3,T4
addr_hit[19]	Covered	T1,T3,T4
addr_hit[20]	Covered	T1,T3,T4
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T3,T4
addr_hit[23]	Covered	T1,T3,T4
addr_hit[24]	Covered	T1,T3,T4
addr_hit[25]	Covered	T1,T3,T4
addr_hit[26]	Covered	T1,T3,T4
addr_hit[27]	Covered	T1,T3,T4
addr_hit[28]	Covered	T1,T3,T4
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T3,T4
addr_hit[31]	Covered	T1,T3,T4
addr_hit[32]	Covered	T1,T3,T4
addr_hit[33]	Covered	T1,T3,T4
addr_hit[34]	Covered	T1,T3,T4
default	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	65357990	1922721	0	0
reAfterRv	65357990	1922721	0	0
rePulse	65357990	1644884	0	0
wePulse	65357990	277837	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	65357990	1922721	0	0
T1	1459	247	0	0
T2	712	3	0	0
T3	2167	142	0	0
T4	8773	336	0	0
T5	5820	407	0	0
T13	35144	4740	0	0
T14	30973	1343	0	0
T15	2264	52	0	0
T16	42484	3964	0	0
T17	1394	10	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	65357990	1922721	0	0
T1	1459	247	0	0
T2	712	3	0	0
T3	2167	142	0	0
T4	8773	336	0	0
T5	5820	407	0	0
T13	35144	4740	0	0
T14	30973	1343	0	0
T15	2264	52	0	0
T16	42484	3964	0	0
T17	1394	10	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	65357990	1644884	0	0
T1	1459	239	0	0
T2	712	2	0	0
T3	2167	91	0	0
T4	8773	200	0	0
T5	5820	215	0	0
T13	35144	4589	0	0
T14	30973	727	0	0
T15	2264	0	0	0
T16	42484	3508	0	0
T17	1394	2	0	0
T34	0	2	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	65357990	277837	0	0
T1	1459	8	0	0
T2	712	1	0	0
T3	2167	51	0	0
T4	8773	136	0	0
T5	5820	192	0	0
T13	35144	151	0	0
T14	30973	616	0	0
T15	2264	52	0	0
T16	42484	456	0	0
T17	1394	8	0	0

Line Coverage for Instance : tb.dut.u_reg_tap

	Line No.	Total	Covered	Percent
TOTAL		227	227	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
CONT_ASSIGN	599	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	671	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	694	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
ALWAYS	1140	36	36	100.00
CONT_ASSIGN	1178	1	1	100.00
ALWAYS	1182	1	1	100.00
CONT_ASSIGN	1221	1	1	100.00
CONT_ASSIGN	1223	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1227	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
CONT_ASSIGN	1231	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1237	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1241	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1251	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1263	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
ALWAYS	1295	36	36	100.00
ALWAYS	1335	53	53	100.00
CONT_ASSIGN	1504	0	0
CONT_ASSIGN	1512	1	1	100.00
CONT_ASSIGN	1513	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut.u_reg_tap

	Total	Covered	Percent
Conditions	278	275	98.92
Logical	278	275	98.92
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
58-1276	98.71
1277-1291	100.00

---

Branch Coverage for Instance : tb.dut.u_reg_tap

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	1178	2	2	100.00
IF	68	3	3	100.00
CASE	1336	36	36	100.00

1178         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T1,T2,T3

68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T68,T100,T81
0	0	Covered	T1,T2,T3

1336           unique case (1'b1)
                      -1-  
1337             addr_hit[0]: begin
1338               reg_rdata_next[0] = '0;
                   ==>
1339               reg_rdata_next[1] = '0;
1340               reg_rdata_next[2] = '0;
1341             end
1342       
1343             addr_hit[1]: begin
1344               reg_rdata_next[0] = status_initialized_qs;
                   ==>
1345               reg_rdata_next[1] = status_ready_qs;
1346               reg_rdata_next[2] = status_ext_clock_switched_qs;
1347               reg_rdata_next[3] = status_transition_successful_qs;
1348               reg_rdata_next[4] = status_transition_count_error_qs;
1349               reg_rdata_next[5] = status_transition_error_qs;
1350               reg_rdata_next[6] = status_token_error_qs;
1351               reg_rdata_next[7] = status_flash_rma_error_qs;
1352               reg_rdata_next[8] = status_otp_error_qs;
1353               reg_rdata_next[9] = status_state_error_qs;
1354               reg_rdata_next[10] = status_bus_integ_error_qs;
1355               reg_rdata_next[11] = status_otp_partition_error_qs;
1356             end
1357       
1358             addr_hit[2]: begin
1359               reg_rdata_next[0] = claim_transition_if_regwen_qs;
                   ==>
1360             end
1361       
1362             addr_hit[3]: begin
1363               reg_rdata_next[7:0] = claim_transition_if_qs;
                   ==>
1364             end
1365       
1366             addr_hit[4]: begin
1367               reg_rdata_next[0] = transition_regwen_qs;
                   ==>
1368             end
1369       
1370             addr_hit[5]: begin
1371               reg_rdata_next[0] = '0;
                   ==>
1372             end
1373       
1374             addr_hit[6]: begin
1375               reg_rdata_next[0] = transition_ctrl_ext_clock_en_qs;
                   ==>
1376               reg_rdata_next[1] = transition_ctrl_volatile_raw_unlock_qs;
1377             end
1378       
1379             addr_hit[7]: begin
1380               reg_rdata_next[31:0] = transition_token_0_qs;
                   ==>
1381             end
1382       
1383             addr_hit[8]: begin
1384               reg_rdata_next[31:0] = transition_token_1_qs;
                   ==>
1385             end
1386       
1387             addr_hit[9]: begin
1388               reg_rdata_next[31:0] = transition_token_2_qs;
                   ==>
1389             end
1390       
1391             addr_hit[10]: begin
1392               reg_rdata_next[31:0] = transition_token_3_qs;
                   ==>
1393             end
1394       
1395             addr_hit[11]: begin
1396               reg_rdata_next[29:0] = transition_target_qs;
                   ==>
1397             end
1398       
1399             addr_hit[12]: begin
1400               reg_rdata_next[31:0] = otp_vendor_test_ctrl_qs;
                   ==>
1401             end
1402       
1403             addr_hit[13]: begin
1404               reg_rdata_next[31:0] = otp_vendor_test_status_qs;
                   ==>
1405             end
1406       
1407             addr_hit[14]: begin
1408               reg_rdata_next[29:0] = lc_state_qs;
                   ==>
1409             end
1410       
1411             addr_hit[15]: begin
1412               reg_rdata_next[4:0] = lc_transition_cnt_qs;
                   ==>
1413             end
1414       
1415             addr_hit[16]: begin
1416               reg_rdata_next[31:0] = lc_id_state_qs;
                   ==>
1417             end
1418       
1419             addr_hit[17]: begin
1420               reg_rdata_next[15:0] = hw_revision0_product_id_qs;
                   ==>
1421               reg_rdata_next[31:16] = hw_revision0_silicon_creator_id_qs;
1422             end
1423       
1424             addr_hit[18]: begin
1425               reg_rdata_next[7:0] = hw_revision1_revision_id_qs;
                   ==>
1426               reg_rdata_next[31:8] = hw_revision1_reserved_qs;
1427             end
1428       
1429             addr_hit[19]: begin
1430               reg_rdata_next[31:0] = device_id_0_qs;
                   ==>
1431             end
1432       
1433             addr_hit[20]: begin
1434               reg_rdata_next[31:0] = device_id_1_qs;
                   ==>
1435             end
1436       
1437             addr_hit[21]: begin
1438               reg_rdata_next[31:0] = device_id_2_qs;
                   ==>
1439             end
1440       
1441             addr_hit[22]: begin
1442               reg_rdata_next[31:0] = device_id_3_qs;
                   ==>
1443             end
1444       
1445             addr_hit[23]: begin
1446               reg_rdata_next[31:0] = device_id_4_qs;
                   ==>
1447             end
1448       
1449             addr_hit[24]: begin
1450               reg_rdata_next[31:0] = device_id_5_qs;
                   ==>
1451             end
1452       
1453             addr_hit[25]: begin
1454               reg_rdata_next[31:0] = device_id_6_qs;
                   ==>
1455             end
1456       
1457             addr_hit[26]: begin
1458               reg_rdata_next[31:0] = device_id_7_qs;
                   ==>
1459             end
1460       
1461             addr_hit[27]: begin
1462               reg_rdata_next[31:0] = manuf_state_0_qs;
                   ==>
1463             end
1464       
1465             addr_hit[28]: begin
1466               reg_rdata_next[31:0] = manuf_state_1_qs;
                   ==>
1467             end
1468       
1469             addr_hit[29]: begin
1470               reg_rdata_next[31:0] = manuf_state_2_qs;
                   ==>
1471             end
1472       
1473             addr_hit[30]: begin
1474               reg_rdata_next[31:0] = manuf_state_3_qs;
                   ==>
1475             end
1476       
1477             addr_hit[31]: begin
1478               reg_rdata_next[31:0] = manuf_state_4_qs;
                   ==>
1479             end
1480       
1481             addr_hit[32]: begin
1482               reg_rdata_next[31:0] = manuf_state_5_qs;
                   ==>
1483             end
1484       
1485             addr_hit[33]: begin
1486               reg_rdata_next[31:0] = manuf_state_6_qs;
                   ==>
1487             end
1488       
1489             addr_hit[34]: begin
1490               reg_rdata_next[31:0] = manuf_state_7_qs;
                   ==>
1491             end
1492       
1493             default: begin
1494               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_tap

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	65357990	236235	0	0
reAfterRv	65357990	236235	0	0
rePulse	65357990	144905	0	0
wePulse	65357990	91330	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	65357990	236235	0	0
T6	20377	96	0	0
T7	18765	119	0	0
T8	22903	143	0	0
T9	0	338	0	0
T10	0	252	0	0
T20	32312	0	0	0
T21	2763	0	0	0
T22	5345	0	0	0
T28	2826	0	0	0
T29	28687	109	0	0
T30	0	247	0	0
T31	0	84	0	0
T32	0	460	0	0
T33	0	584	0	0
T35	1397	0	0	0
T36	1828	0	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	65357990	236235	0	0
T6	20377	96	0	0
T7	18765	119	0	0
T8	22903	143	0	0
T9	0	338	0	0
T10	0	252	0	0
T20	32312	0	0	0
T21	2763	0	0	0
T22	5345	0	0	0
T28	2826	0	0	0
T29	28687	109	0	0
T30	0	247	0	0
T31	0	84	0	0
T32	0	460	0	0
T33	0	584	0	0
T35	1397	0	0	0
T36	1828	0	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	65357990	144905	0	0
T6	20377	49	0	0
T7	18765	48	0	0
T8	22903	79	0	0
T9	0	185	0	0
T10	0	138	0	0
T20	32312	0	0	0
T21	2763	0	0	0
T22	5345	0	0	0
T28	2826	0	0	0
T29	28687	61	0	0
T30	0	111	0	0
T31	0	42	0	0
T32	0	375	0	0
T33	0	293	0	0
T35	1397	0	0	0
T36	1828	0	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	65357990	91330	0	0
T6	20377	47	0	0
T7	18765	71	0	0
T8	22903	64	0	0
T9	0	153	0	0
T10	0	114	0	0
T20	32312	0	0	0
T21	2763	0	0	0
T22	5345	0	0	0
T28	2826	0	0	0
T29	28687	48	0	0
T30	0	136	0	0
T31	0	42	0	0
T32	0	85	0	0
T33	0	291	0	0
T35	1397	0	0	0
T36	1828	0	0	0