Line Coverage for Module :
lc_ctrl_kmac_if
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 41 | 41 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| ALWAYS | 88 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 102 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 103 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 104 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 107 | 1 | 1 | 100.00 |
| ALWAYS | 159 | 21 | 21 | 100.00 |
| ALWAYS | 203 | 3 | 3 | 100.00 |
| ALWAYS | 206 | 3 | 3 | 100.00 |
43 lc_token_t kmac_transition_token;
44 1/1 assign kmac_transition_token = transition_token_i;
Tests: T1 T2 T3
45
46 // SRC domain cannot change data while waiting for ACK.
47 `ASSERT(DataStable_A, token_hash_req_i && !token_hash_ack_o |-> $stable(transition_token_i))
48
49 // Second synchronizer instance for handshake and return data synchronization.
50 logic kmac_req, kmac_ack;
51 logic token_hash_req;
52 logic token_hash_ack_d, token_hash_ack_q;
53 logic token_hash_err_q, token_hash_err_d;
54 lc_token_t hashed_token_q, hashed_token_d;
55 prim_sync_reqack_data #(
56 // Token + Error bit
57 .Width (LcTokenWidth + 1),
58 .DataSrc2Dst(1'b0),
59 // This instantiates a data register
60 // on the destination side.
61 .DataReg (1'b1)
62 ) u_prim_sync_reqack_data_in (
63 .clk_src_i ( clk_i ),
64 .rst_src_ni ( rst_ni ),
65 .clk_dst_i ( clk_kmac_i ),
66 .rst_dst_ni ( rst_kmac_ni ),
67 .req_chk_i ( token_hash_req_chk_i ),
68 .src_req_i ( token_hash_req ),
69 .src_ack_o ( token_hash_ack_d ),
70 .dst_req_o ( kmac_req ),
71 .dst_ack_i ( kmac_ack ),
72 // Truncate hash to 128bit and remove masking (not required here).
73 .data_i ( {kmac_data_i.error,
74 kmac_data_i.digest_share0[LcTokenWidth-1:0] ^
75 kmac_data_i.digest_share1[LcTokenWidth-1:0]} ),
76 .data_o ( {token_hash_err_d,
77 hashed_token_d} )
78 );
79
80 logic unused_sigs;
81 1/1 assign unused_sigs = ^{
Tests: T1 T2 T3
82 kmac_data_i.digest_share0[LcTokenWidth +: (kmac_pkg::AppDigestW - LcTokenWidth)],
83 kmac_data_i.digest_share1[LcTokenWidth +: (kmac_pkg::AppDigestW - LcTokenWidth)]
84 };
85
86 // Hashed Token Register Running on LC Clock
87 always_ff @(posedge clk_i or negedge rst_ni) begin : p_lc_regs
88 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
89 1/1 token_hash_ack_q <= 1'b0;
Tests: T1 T2 T3
90 1/1 token_hash_err_q <= 1'b0;
Tests: T1 T2 T3
91 1/1 hashed_token_q <= {LcTokenWidth{1'b1}};
Tests: T1 T2 T3
92 end else begin
93 1/1 token_hash_ack_q <= token_hash_ack_d;
Tests: T1 T2 T3
94 // Latch synchronized token and error bit
95 1/1 if (token_hash_req_i && token_hash_ack_d) begin
Tests: T1 T2 T3
96 1/1 token_hash_err_q <= token_hash_err_d;
Tests: T1 T3 T5
97 1/1 hashed_token_q <= hashed_token_d;
Tests: T1 T3 T5
98 end
MISSING_ELSE
99 end
100 end
101
102 1/1 assign token_hash_ack_o = token_hash_ack_q;
Tests: T1 T2 T3
103 1/1 assign token_hash_err_o = token_hash_err_q;
Tests: T1 T2 T3
104 1/1 assign hashed_token_o = hashed_token_q;
Tests: T1 T2 T3
105
106 // Stop requesting tokens upon latching on LC side.
107 1/1 assign token_hash_req = token_hash_req_i & ~token_hash_ack_q;
Tests: T1 T2 T3
108
109 // Need to synchronize this error signal separately.
110 logic kmac_fsm_err_d, kmac_fsm_err_q;
111 prim_flop_2sync #(
112 .Width(1),
113 .ResetValue(0)
114 ) u_prim_flop_2sync (
115 .clk_i,
116 .rst_ni,
117 .d_i(kmac_fsm_err_q),
118 .q_o(token_if_fsm_err_o)
119 );
120
121 /////////////////////////////////////////////
122 // Serialization FSM Running on KMAC Clock //
123 /////////////////////////////////////////////
124
125 // SEC_CM: KMAC.FSM.SPARSE
126 // Encoding generated with:
127 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 4 -n 8 \
128 // -s 3343913945 --language=sv
129 //
130 // Hamming distance histogram:
131 //
132 // 0: --
133 // 1: --
134 // 2: --
135 // 3: --
136 // 4: --
137 // 5: |||||||||||||||||||| (66.67%)
138 // 6: |||||||||| (33.33%)
139 // 7: --
140 // 8: --
141 //
142 // Minimum Hamming distance: 5
143 // Maximum Hamming distance: 6
144 // Minimum Hamming weight: 2
145 // Maximum Hamming weight: 6
146 //
147 localparam int StateWidth = 8;
148 typedef enum logic [StateWidth-1:0] {
149 FirstSt = 8'b01011011,
150 SecondSt = 8'b10010100,
151 WaitSt = 8'b11100111,
152 DoneSt = 8'b00101000
153 } state_e;
154
155 state_e state_d, state_q;
156
157 // Serialize the 128bit token into two 64bit beats.
158 always_comb begin : p_kmac
159 1/1 state_d = state_q;
Tests: T1 T2 T3
160 1/1 kmac_data_o = '0;
Tests: T1 T2 T3
161 1/1 kmac_ack = 1'b0;
Tests: T1 T2 T3
162 1/1 kmac_fsm_err_d = 1'b0;
Tests: T1 T2 T3
163
164 1/1 unique case (state_q)
Tests: T1 T2 T3
165 // Wait for request and transfer first half of
166 // LC token.
167 FirstSt: begin
168 1/1 if (kmac_req) begin
Tests: T1 T2 T3
169 1/1 kmac_data_o.valid = 1'b1;
Tests: T1 T3 T5
170 1/1 kmac_data_o.strb = 8'hFF;
Tests: T1 T3 T5
171 1/1 kmac_data_o.data = kmac_transition_token[0 +: 64];
Tests: T1 T3 T5
172 1/1 if (kmac_data_i.ready) begin
Tests: T1 T3 T5
173 1/1 state_d = SecondSt;
Tests: T1 T3 T5
174 end
MISSING_ELSE
175 end
MISSING_ELSE
176 end
177 // Transfer second half of LC token.
178 SecondSt: begin
179 1/1 kmac_data_o.valid = 1'b1;
Tests: T1 T3 T5
180 1/1 kmac_data_o.strb = 8'hFF;
Tests: T1 T3 T5
181 1/1 kmac_data_o.last = 1'b1;
Tests: T1 T3 T5
182 1/1 kmac_data_o.data = kmac_transition_token[64 +: 64];
Tests: T1 T3 T5
183 1/1 if (kmac_data_i.ready) begin
Tests: T1 T3 T5
184 1/1 state_d = WaitSt;
Tests: T1 T3 T5
185 end
MISSING_ELSE
186 end
187 // Wait for hashed token response and go to terminal state.
188 WaitSt: begin
189 1/1 if (kmac_data_i.done) begin
Tests: T1 T3 T5
190 1/1 kmac_ack = 1'b1;
Tests: T1 T3 T5
191 1/1 state_d = DoneSt;
Tests: T1 T3 T5
192 end
MISSING_ELSE
193 end
194 // Terminal state (by design we can only perform
195 // one token hashing operation per reset cycle).
196 1/1 DoneSt: ;
Tests: T1 T3 T5
197 default: begin
198 kmac_fsm_err_d = 1'b1;
199 end
200 endcase // state_q
201 end
202
203 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, FirstSt, clk_kmac_i, rst_kmac_ni)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, FirstSt, clk_kmac_i, rst_kmac_ni):
203.1 `ifdef SIMULATION
203.2 prim_sparse_fsm_flop #(
203.3 .StateEnumT(state_e),
203.4 .Width($bits(state_e)),
203.5 .ResetValue($bits(state_e)'(FirstSt)),
203.6 .EnableAlertTriggerSVA(1),
203.7 .CustomForceName("state_q")
203.8 ) u_state_regs (
203.9 .clk_i ( clk_kmac_i ),
203.10 .rst_ni ( rst_kmac_ni ),
203.11 .state_i ( state_d ),
203.12 .state_o ( )
203.13 );
203.14 always_ff @(posedge clk_kmac_i or negedge rst_kmac_ni) begin
203.15 1/1 if (!rst_kmac_ni) begin
Tests: T1 T2 T3
203.16 1/1 state_q <= FirstSt;
Tests: T1 T2 T3
203.17 end else begin
203.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
203.19 end
203.20 end
203.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
203.22 else begin
203.23 `ifdef UVM
203.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
203.25 "../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv", 203, "", 1);
203.26 `else
203.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
203.28 `PRIM_STRINGIFY(u_state_regs_A));
203.29 `endif
203.30 end
203.31 `else
203.32 prim_sparse_fsm_flop #(
203.33 .StateEnumT(state_e),
203.34 .Width($bits(state_e)),
203.35 .ResetValue($bits(state_e)'(FirstSt)),
203.36 .EnableAlertTriggerSVA(1)
203.37 ) u_state_regs (
203.38 .clk_i ( clk_kmac_i ),
203.39 .rst_ni ( rst_kmac_ni ),
203.40 .state_i ( state_d ),
203.41 .state_o ( state_q )
203.42 );
203.43 `endif204
205 always_ff @(posedge clk_kmac_i or negedge rst_kmac_ni) begin : p_kmac_fsm_err
206 1/1 if (!rst_kmac_ni) begin
Tests: T1 T2 T3
207 1/1 kmac_fsm_err_q <= 1'b0;
Tests: T1 T2 T3
208 end else begin
209 1/1 kmac_fsm_err_q <= kmac_fsm_err_d;
Tests: T1 T2 T3
Cond Coverage for Module :
lc_ctrl_kmac_if
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 95
EXPRESSION (token_hash_req_i && token_hash_ack_d)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T14,T45,T63 |
| 1 | 0 | Covered | T1,T3,T5 |
| 1 | 1 | Covered | T1,T3,T5 |
LINE 107
EXPRESSION (token_hash_req_i & ((~token_hash_ack_q)))
--------1------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T5 |
| 1 | 1 | Covered | T1,T3,T5 |
FSM Coverage for Module :
lc_ctrl_kmac_if
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DoneSt |
191 |
Covered |
T1,T3,T5 |
| FirstSt |
203 |
Covered |
T1,T2,T3 |
| SecondSt |
173 |
Covered |
T1,T3,T5 |
| WaitSt |
184 |
Covered |
T1,T3,T5 |
| transitions | Line No. | Covered | Tests |
| DoneSt->FirstSt |
203 |
Covered |
T3,T5,T13 |
| FirstSt->SecondSt |
173 |
Covered |
T1,T3,T5 |
| SecondSt->FirstSt |
203 |
Covered |
T67 |
| SecondSt->WaitSt |
184 |
Covered |
T1,T3,T5 |
| WaitSt->DoneSt |
191 |
Covered |
T1,T3,T5 |
| WaitSt->FirstSt |
203 |
Covered |
T177 |
Branch Coverage for Module :
lc_ctrl_kmac_if
| Line No. | Total | Covered | Percent |
| Branches |
|
16 |
16 |
100.00 |
| IF |
88 |
3 |
3 |
100.00 |
| CASE |
164 |
9 |
9 |
100.00 |
| IF |
203 |
2 |
2 |
100.00 |
| IF |
206 |
2 |
2 |
100.00 |
88 if (!rst_ni) begin
-1-
89 token_hash_ack_q <= 1'b0;
==>
90 token_hash_err_q <= 1'b0;
91 hashed_token_q <= {LcTokenWidth{1'b1}};
92 end else begin
93 token_hash_ack_q <= token_hash_ack_d;
94 // Latch synchronized token and error bit
95 if (token_hash_req_i && token_hash_ack_d) begin
-2-
96 token_hash_err_q <= token_hash_err_d;
==>
97 hashed_token_q <= hashed_token_d;
98 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T3,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
164 unique case (state_q)
-1-
165 // Wait for request and transfer first half of
166 // LC token.
167 FirstSt: begin
168 if (kmac_req) begin
-2-
169 kmac_data_o.valid = 1'b1;
170 kmac_data_o.strb = 8'hFF;
171 kmac_data_o.data = kmac_transition_token[0 +: 64];
172 if (kmac_data_i.ready) begin
-3-
173 state_d = SecondSt;
==>
174 end
MISSING_ELSE
==>
175 end
MISSING_ELSE
==>
176 end
177 // Transfer second half of LC token.
178 SecondSt: begin
179 kmac_data_o.valid = 1'b1;
180 kmac_data_o.strb = 8'hFF;
181 kmac_data_o.last = 1'b1;
182 kmac_data_o.data = kmac_transition_token[64 +: 64];
183 if (kmac_data_i.ready) begin
-4-
184 state_d = WaitSt;
==>
185 end
MISSING_ELSE
==>
186 end
187 // Wait for hashed token response and go to terminal state.
188 WaitSt: begin
189 if (kmac_data_i.done) begin
-5-
190 kmac_ack = 1'b1;
==>
191 state_d = DoneSt;
192 end
MISSING_ELSE
==>
193 end
194 // Terminal state (by design we can only perform
195 // one token hashing operation per reset cycle).
196 DoneSt: ;
==>
197 default: begin
198 kmac_fsm_err_d = 1'b1;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
| FirstSt |
1 |
1 |
- |
- |
Covered |
T1,T3,T5 |
| FirstSt |
1 |
0 |
- |
- |
Covered |
T1,T5,T13 |
| FirstSt |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
| SecondSt |
- |
- |
1 |
- |
Covered |
T1,T3,T5 |
| SecondSt |
- |
- |
0 |
- |
Covered |
T1,T5,T13 |
| WaitSt |
- |
- |
- |
1 |
Covered |
T1,T3,T5 |
| WaitSt |
- |
- |
- |
0 |
Covered |
T1,T3,T5 |
| DoneSt |
- |
- |
- |
- |
Covered |
T1,T3,T5 |
| default |
- |
- |
- |
- |
Covered |
T5,T50,T51 |
203 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, FirstSt, clk_kmac_i, rst_kmac_ni)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
206 if (!rst_kmac_ni) begin
-1-
207 kmac_fsm_err_q <= 1'b0;
==>
208 end else begin
209 kmac_fsm_err_q <= kmac_fsm_err_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
lc_ctrl_kmac_if
Assertion Details
DataStable_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
63056971 |
21267583 |
0 |
0 |
| T1 |
1459 |
161 |
0 |
0 |
| T2 |
712 |
0 |
0 |
0 |
| T3 |
2167 |
133 |
0 |
0 |
| T4 |
8773 |
0 |
0 |
0 |
| T5 |
5820 |
438 |
0 |
0 |
| T7 |
0 |
82 |
0 |
0 |
| T13 |
35144 |
32030 |
0 |
0 |
| T14 |
30973 |
575 |
0 |
0 |
| T15 |
2264 |
0 |
0 |
0 |
| T16 |
42484 |
25392 |
0 |
0 |
| T17 |
1394 |
15 |
0 |
0 |
| T21 |
0 |
117 |
0 |
0 |
| T22 |
0 |
587 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
61424643 |
58345686 |
0 |
0 |
| T1 |
1459 |
1397 |
0 |
0 |
| T2 |
712 |
641 |
0 |
0 |
| T3 |
2167 |
1694 |
0 |
0 |
| T4 |
8773 |
7516 |
0 |
0 |
| T5 |
5138 |
4199 |
0 |
0 |
| T13 |
35144 |
34440 |
0 |
0 |
| T14 |
30973 |
24808 |
0 |
0 |
| T15 |
2264 |
2203 |
0 |
0 |
| T16 |
42484 |
38300 |
0 |
0 |
| T17 |
1394 |
1333 |
0 |
0 |
