Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	65357990	15383	0	0
claim_transition_if_regwen_rd_A	65357990	1376	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	65357990	15383	0	0
T66	32887	0	0	0
T99	182944	0	0	0
T101	164915	3	0	0
T103	0	7	0	0
T148	0	18	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	8	0	0
T152	0	11	0	0
T153	0	3	0	0
T154	0	12	0	0
T155	0	1	0	0
T156	1732	0	0	0
T157	5578	0	0	0
T158	32052	0	0	0
T159	826	0	0	0
T160	2143	0	0	0
T161	11988	0	0	0
T162	18608	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	65357990	1376	0	0
T40	63208	0	0	0
T102	248547	6	0	0
T103	0	11	0	0
T114	0	7	0	0
T146	0	16	0	0
T163	0	5	0	0
T164	0	9	0	0
T165	0	10	0	0
T166	0	8	0	0
T167	0	8	0	0
T168	0	124	0	0
T169	28303	0	0	0
T170	7362	0	0	0
T171	1297	0	0	0
T172	34002	0	0	0
T173	25211	0	0	0
T174	137300	0	0	0
T175	25543	0	0	0
T176	26704	0	0	0