Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	745778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

934139

1

T1

2

T2

7

T3

409

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1387343	1			T1	2		T2	97		T3	658
values[0x0]	145885	1			T1	1		T2	6		T3	48
values[0x1]	146689	1			T2	2		T3	47		T6	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	589243	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1090674

1

T1

2

T2

36

T3

474

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5371	1			T3	2		T5	1		T15	2
valid_sources[0x01]	5736	1			T4	2		T15	4		T8	1
valid_sources[0x02]	5705	1			T4	1		T15	2		T33	2
valid_sources[0x03]	5516	1			T3	4		T4	3		T5	5
valid_sources[0x04]	5550	1			T2	4		T3	5		T4	1
valid_sources[0x05]	5637	1			T3	8		T4	4		T5	9
valid_sources[0x06]	5756	1			T3	2		T15	3		T8	1
valid_sources[0x07]	5731	1			T3	1		T4	1		T5	1
valid_sources[0x08]	5452	1			T3	1		T15	4		T20	8
valid_sources[0x09]	5594	1			T3	3		T5	2		T15	8
valid_sources[0x0a]	6307	1			T2	2		T3	4		T15	4
valid_sources[0x0b]	5729	1			T3	6		T15	2		T8	1
valid_sources[0x0c]	5267	1			T2	2		T4	2		T5	1
valid_sources[0x0d]	6404	1			T3	5		T4	2		T15	9
valid_sources[0x0e]	5484	1			T15	4		T20	3		T23	9
valid_sources[0x0f]	7477	1			T2	2		T3	4		T15	2
valid_sources[0x10]	5468	1			T2	3		T3	6		T6	1
valid_sources[0x11]	7818	1			T3	2		T4	7		T15	7
valid_sources[0x12]	12807	1			T1	1		T3	1		T6	2
valid_sources[0x13]	5992	1			T4	1		T5	4		T22	4
valid_sources[0x14]	5518	1			T3	2		T6	1		T4	1
valid_sources[0x15]	5565	1			T3	1		T4	1		T15	5
valid_sources[0x16]	5547	1			T3	3		T15	3		T22	5
valid_sources[0x17]	5501	1			T6	2		T4	1		T15	1
valid_sources[0x18]	9860	1			T3	1		T4	1		T5	1
valid_sources[0x19]	5466	1			T6	1		T4	5		T15	8
valid_sources[0x1a]	5528	1			T3	1		T15	2		T22	2
valid_sources[0x1b]	6238	1			T3	9		T15	2		T20	1
valid_sources[0x1c]	5454	1			T3	2		T4	1		T5	9
valid_sources[0x1d]	5986	1			T1	1		T3	1		T5	13
valid_sources[0x1e]	5933	1			T3	4		T12	1		T15	2
valid_sources[0x1f]	5255	1			T2	2		T14	1		T15	9
valid_sources[0x20]	5708	1			T3	1		T15	7		T8	1
valid_sources[0x21]	5430	1			T3	7		T6	1		T15	3
valid_sources[0x22]	7955	1			T2	1		T15	3		T22	1
valid_sources[0x23]	5415	1			T3	1		T15	2		T8	1
valid_sources[0x24]	5209	1			T3	1		T15	4		T23	11
valid_sources[0x25]	5703	1			T6	3		T15	6		T8	1
valid_sources[0x26]	6590	1			T3	3		T4	3		T15	5
valid_sources[0x27]	7029	1			T3	1		T4	1		T15	2
valid_sources[0x28]	5375	1			T4	2		T15	1		T22	5
valid_sources[0x29]	6535	1			T22	1		T8	1		T20	5
valid_sources[0x2a]	5391	1			T3	3		T4	2		T15	4
valid_sources[0x2b]	6091	1			T3	3		T4	1		T5	1
valid_sources[0x2c]	5721	1			T3	2		T15	6		T22	1
valid_sources[0x2d]	5637	1			T3	11		T6	3		T4	4
valid_sources[0x2e]	7280	1			T4	1		T15	5		T20	4
valid_sources[0x2f]	5580	1			T3	4		T15	3		T22	1
valid_sources[0x30]	9119	1			T3	1		T4	1		T12	1
valid_sources[0x31]	6580	1			T3	2		T5	2		T15	6
valid_sources[0x32]	7600	1			T3	1		T15	3		T22	5
valid_sources[0x33]	6317	1			T3	4		T5	4		T15	5
valid_sources[0x34]	7073	1			T15	1		T22	6		T8	1
valid_sources[0x35]	5142	1			T3	1		T4	2		T15	2
valid_sources[0x36]	15343	1			T3	3		T6	1		T4	3
valid_sources[0x37]	8049	1			T2	5		T3	1		T4	2
valid_sources[0x38]	5804	1			T2	1		T3	9		T15	2
valid_sources[0x39]	7198	1			T2	4		T3	6		T6	1
valid_sources[0x3a]	5550	1			T4	3		T15	7		T20	1
valid_sources[0x3b]	5530	1			T2	2		T3	7		T4	1
valid_sources[0x3c]	5623	1			T3	1		T6	1		T15	4
valid_sources[0x3d]	6087	1			T3	1		T4	3		T15	5
valid_sources[0x3e]	5551	1			T15	2		T22	1		T8	1
valid_sources[0x3f]	5354	1			T3	5		T15	12		T22	1
valid_sources[0x40]	5872	1			T2	2		T3	2		T4	5
valid_sources[0x41]	5774	1			T3	3		T5	1		T15	7
valid_sources[0x42]	5487	1			T2	2		T3	4		T6	1
valid_sources[0x43]	54026	1			T2	1		T3	2		T6	2
valid_sources[0x44]	6357	1			T3	9		T15	3		T20	2
valid_sources[0x45]	5517	1			T4	2		T5	5		T15	4
valid_sources[0x46]	5488	1			T2	1		T3	4		T15	4
valid_sources[0x47]	5770	1			T2	1		T3	3		T15	4
valid_sources[0x48]	5609	1			T2	1		T3	9		T4	3
valid_sources[0x49]	6057	1			T3	1		T5	1		T15	2
valid_sources[0x4a]	5215	1			T2	1		T3	6		T4	1
valid_sources[0x4b]	7109	1			T3	8		T4	5		T15	3
valid_sources[0x4c]	5634	1			T22	1		T8	1		T29	4
valid_sources[0x4d]	5485	1			T3	3		T15	2		T22	2
valid_sources[0x4e]	5561	1			T4	10		T15	3		T8	1
valid_sources[0x4f]	5773	1			T2	1		T6	2		T5	19
valid_sources[0x50]	5606	1			T4	1		T5	4		T15	5
valid_sources[0x51]	5702	1			T3	3		T15	2		T20	3
valid_sources[0x52]	6984	1			T3	2		T6	1		T29	11
valid_sources[0x53]	5473	1			T2	1		T3	2		T4	1
valid_sources[0x54]	5795	1			T3	1		T4	2		T20	1
valid_sources[0x55]	6011	1			T3	6		T15	4		T23	28
valid_sources[0x56]	6814	1			T4	3		T15	3		T20	1
valid_sources[0x57]	8719	1			T3	6		T15	3		T20	2
valid_sources[0x58]	5401	1			T3	2		T4	1		T15	1
valid_sources[0x59]	5423	1			T3	6		T4	1		T15	1
valid_sources[0x5a]	5480	1			T3	1		T15	9		T8	1
valid_sources[0x5b]	5586	1			T3	5		T4	1		T14	2
valid_sources[0x5c]	5804	1			T15	3		T31	17		T23	25
valid_sources[0x5d]	5520	1			T2	1		T3	3		T15	3
valid_sources[0x5e]	6835	1			T2	3		T4	1		T15	6
valid_sources[0x5f]	9335	1			T3	2		T15	6		T22	2
valid_sources[0x60]	5420	1			T5	7		T15	5		T20	1
valid_sources[0x61]	7165	1			T2	1		T3	3		T4	1
valid_sources[0x62]	7850	1			T3	3		T6	1		T4	1
valid_sources[0x63]	7052	1			T3	2		T5	1		T22	1
valid_sources[0x64]	5417	1			T3	1		T6	2		T5	1
valid_sources[0x65]	6475	1			T3	3		T5	3		T15	3
valid_sources[0x66]	5282	1			T3	1		T4	1		T12	1
valid_sources[0x67]	5518	1			T3	2		T4	1		T5	6
valid_sources[0x68]	5649	1			T2	1		T3	6		T4	10
valid_sources[0x69]	5289	1			T3	6		T15	11		T23	11
valid_sources[0x6a]	28628	1			T6	2		T15	11		T22	7
valid_sources[0x6b]	5334	1			T3	8		T6	2		T5	9
valid_sources[0x6c]	6962	1			T4	1		T15	1		T22	6
valid_sources[0x6d]	5616	1			T3	5		T4	2		T15	6
valid_sources[0x6e]	5654	1			T3	2		T4	1		T5	1
valid_sources[0x6f]	7629	1			T3	3		T4	3		T15	3
valid_sources[0x70]	8513	1			T2	1		T4	1		T15	1
valid_sources[0x71]	6574	1			T5	1		T15	7		T22	1
valid_sources[0x72]	5352	1			T3	9		T5	9		T15	8
valid_sources[0x73]	5728	1			T3	3		T15	8		T22	1
valid_sources[0x74]	8894	1			T3	1		T4	2		T15	2
valid_sources[0x75]	6373	1			T3	4		T15	3		T22	1
valid_sources[0x76]	8113	1			T6	1		T5	8		T15	2
valid_sources[0x77]	5375	1			T3	7		T6	1		T4	1
valid_sources[0x78]	5383	1			T2	3		T5	2		T15	2
valid_sources[0x79]	6887	1			T2	1		T3	5		T12	1
valid_sources[0x7a]	6645	1			T3	2		T5	2		T15	4
valid_sources[0x7b]	5608	1			T3	1		T6	1		T4	4
valid_sources[0x7c]	7227	1			T2	1		T3	3		T6	2
valid_sources[0x7d]	5686	1			T2	1		T3	2		T6	1
valid_sources[0x7e]	5130	1			T3	1		T4	2		T15	2
valid_sources[0x7f]	5430	1			T15	4		T22	3		T20	1
valid_sources[0x80]	6822	1			T3	8		T15	4		T19	876

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

682140

1

T1

2

T3

330

T6

17

values[0x0]

all_enables

biggest_size

126584

1

T2

6

T3

39

T6

12

values[0x1]

all_enables

biggest_size

125415

1

T2

1

T3

40

T6

13