Unified Coverage Report :: Module :: prim_sparse_fsm_flop

Module : prim_sparse_fsm_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_kmac_if.u_state_regs	100.00	100.00					100.00
tb.dut.u_lc_ctrl_fsm.u_fsm_state_regs	100.00	100.00					100.00
tb.dut.u_lc_ctrl_fsm.u_state_regs	100.00	100.00					100.00
tb.dut.u_lc_ctrl_fsm.u_cnt_regs	100.00	100.00					100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00		100.00	100.00	100.00	u_lc_ctrl_kmac_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_fsm_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.67	98.17	91.67		100.00	98.53	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.67	98.17	91.67		100.00	98.53	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_cnt_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.67	98.17	91.67		100.00	98.53	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

Line Coverage for Module : prim_sparse_fsm_flop

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Module : prim_sparse_fsm_flop

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	3308	3308	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308	3308	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T12	4	4	0	0
T13	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	827	827	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_fsm_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_fsm_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	827	827	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	827	827	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_cnt_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_cnt_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	827	827	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0