Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	63215830	15085	0	0
claim_transition_if_regwen_rd_A	63215830	1559	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63215830	15085	0	0
T49	0	1	0	0
T59	17698	0	0	0
T63	21576	0	0	0
T64	24453	0	0	0
T69	74322	5	0	0
T79	2830	0	0	0
T103	0	3	0	0
T104	0	7	0	0
T110	23813	0	0	0
T111	64048	0	0	0
T112	1910	0	0	0
T113	974	0	0	0
T114	24206	0	0	0
T156	0	10	0	0
T157	0	6	0	0
T158	0	12	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	7	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63215830	1559	0	0
T42	41469	0	0	0
T104	277417	7	0	0
T118	0	2	0	0
T122	0	12	0	0
T159	0	15	0	0
T160	0	3	0	0
T162	0	9	0	0
T163	0	3	0	0
T164	0	8	0	0
T165	0	7	0	0
T166	0	2	0	0
T167	6881	0	0	0
T168	3469	0	0	0
T169	237010	0	0	0
T170	80187	0	0	0
T171	152970	0	0	0
T172	41403	0	0	0
T173	21979	0	0	0
T174	11995	0	0	0