Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	808434	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

995432

1

T1

6

T2

56

T3

2144

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1514461	1			T1	25		T2	55		T3	4206
values[0x0]	143896	1			T1	6		T2	14		T3	40
values[0x1]	145509	1			T1	2		T2	18		T3	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	639036	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1164830

1

T1

16

T2

66

T3

2575

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6119	1			T3	21		T14	37		T15	2
valid_sources[0x01]	6654	1			T3	42		T14	68		T15	8
valid_sources[0x02]	6580	1			T2	4		T3	6		T14	30
valid_sources[0x03]	5457	1			T2	1		T3	26		T4	7
valid_sources[0x04]	5568	1			T3	8		T4	15		T14	37
valid_sources[0x05]	5651	1			T3	10		T14	69		T15	12
valid_sources[0x06]	5473	1			T3	14		T14	30		T15	6
valid_sources[0x07]	5742	1			T3	22		T14	33		T15	4
valid_sources[0x08]	5504	1			T3	19		T14	71		T15	9
valid_sources[0x09]	5628	1			T3	15		T14	28		T15	8
valid_sources[0x0a]	6835	1			T3	14		T4	10		T14	33
valid_sources[0x0b]	5496	1			T3	13		T14	55		T15	7
valid_sources[0x0c]	5676	1			T3	60		T14	34		T15	10
valid_sources[0x0d]	8005	1			T3	15		T14	44		T15	8
valid_sources[0x0e]	5777	1			T3	29		T4	3		T14	24
valid_sources[0x0f]	5879	1			T3	21		T14	23		T15	4
valid_sources[0x10]	6391	1			T3	25		T4	28		T14	28
valid_sources[0x11]	5768	1			T3	33		T14	24		T15	12
valid_sources[0x12]	6580	1			T3	10		T14	47		T15	6
valid_sources[0x13]	5895	1			T3	12		T14	34		T15	3
valid_sources[0x14]	5817	1			T3	15		T14	22		T15	5
valid_sources[0x15]	9044	1			T3	10		T14	38		T15	7
valid_sources[0x16]	5318	1			T3	33		T14	55		T15	4
valid_sources[0x17]	5430	1			T3	17		T14	38		T15	2
valid_sources[0x18]	5231	1			T3	7		T14	26		T15	11
valid_sources[0x19]	5678	1			T3	13		T4	7		T14	56
valid_sources[0x1a]	5396	1			T3	23		T14	49		T15	5
valid_sources[0x1b]	5457	1			T2	2		T3	60		T4	18
valid_sources[0x1c]	5591	1			T3	3		T14	22		T15	6
valid_sources[0x1d]	5547	1			T3	3		T14	33		T15	3
valid_sources[0x1e]	5574	1			T3	25		T14	53		T15	2
valid_sources[0x1f]	7219	1			T3	86		T4	4		T14	31
valid_sources[0x20]	5514	1			T3	27		T14	24		T15	11
valid_sources[0x21]	8419	1			T3	30		T14	46		T17	7
valid_sources[0x22]	5357	1			T3	32		T14	47		T15	1
valid_sources[0x23]	5632	1			T3	10		T14	43		T15	9
valid_sources[0x24]	15474	1			T3	26		T14	35		T15	13
valid_sources[0x25]	5620	1			T3	14		T4	3		T14	35
valid_sources[0x26]	5495	1			T2	8		T3	60		T14	53
valid_sources[0x27]	5564	1			T3	34		T14	25		T15	4
valid_sources[0x28]	6942	1			T3	8		T14	24		T15	6
valid_sources[0x29]	5781	1			T3	8		T14	52		T15	5
valid_sources[0x2a]	5984	1			T2	1		T3	49		T14	43
valid_sources[0x2b]	5751	1			T3	22		T14	60		T15	12
valid_sources[0x2c]	7924	1			T1	2		T3	15		T13	2336
valid_sources[0x2d]	5578	1			T2	1		T4	7		T14	51
valid_sources[0x2e]	5562	1			T3	23		T14	29		T15	11
valid_sources[0x2f]	5522	1			T14	42		T15	10		T6	2
valid_sources[0x30]	5649	1			T3	7		T4	4		T14	40
valid_sources[0x31]	7122	1			T2	2		T3	5		T4	7
valid_sources[0x32]	5869	1			T3	21		T14	26		T15	5
valid_sources[0x33]	5422	1			T1	1		T3	35		T14	32
valid_sources[0x34]	8001	1			T3	8		T14	27		T15	1
valid_sources[0x35]	5638	1			T1	1		T2	3		T3	28
valid_sources[0x36]	6681	1			T3	20		T4	2		T14	51
valid_sources[0x37]	7776	1			T3	1		T14	32		T15	5
valid_sources[0x38]	12724	1			T3	6		T4	8		T14	60
valid_sources[0x39]	5565	1			T3	1		T14	31		T15	4
valid_sources[0x3a]	7299	1			T3	3		T14	25		T15	3
valid_sources[0x3b]	6836	1			T3	38		T14	47		T15	2
valid_sources[0x3c]	9360	1			T3	4		T14	48		T15	5
valid_sources[0x3d]	5746	1			T3	19		T14	33		T15	2
valid_sources[0x3e]	8921	1			T14	23		T15	3		T17	8
valid_sources[0x3f]	5515	1			T1	1		T3	5		T4	2
valid_sources[0x40]	7255	1			T3	17		T14	68		T15	13
valid_sources[0x41]	5862	1			T3	17		T14	43		T15	12
valid_sources[0x42]	6161	1			T3	31		T14	51		T15	11
valid_sources[0x43]	5482	1			T3	25		T4	5		T14	30
valid_sources[0x44]	7149	1			T14	28		T15	6		T7	1
valid_sources[0x45]	5933	1			T3	5		T14	46		T15	8
valid_sources[0x46]	5560	1			T3	6		T14	47		T15	15
valid_sources[0x47]	7114	1			T3	11		T14	37		T15	3
valid_sources[0x48]	5683	1			T1	2		T3	19		T14	25
valid_sources[0x49]	5290	1			T3	14		T14	38		T15	8
valid_sources[0x4a]	5713	1			T3	30		T4	8		T14	45
valid_sources[0x4b]	5860	1			T3	9		T14	76		T15	5
valid_sources[0x4c]	6645	1			T14	56		T15	6		T17	3
valid_sources[0x4d]	5541	1			T3	5		T14	27		T15	5
valid_sources[0x4e]	5848	1			T2	1		T3	4		T4	9
valid_sources[0x4f]	5197	1			T3	28		T4	2		T14	11
valid_sources[0x50]	6137	1			T3	20		T14	56		T15	9
valid_sources[0x51]	5246	1			T2	1		T3	19		T14	33
valid_sources[0x52]	9187	1			T14	26		T15	3		T17	10
valid_sources[0x53]	5227	1			T3	2		T14	37		T15	13
valid_sources[0x54]	5471	1			T1	2		T3	2		T14	54
valid_sources[0x55]	9225	1			T3	6		T4	9		T14	45
valid_sources[0x56]	10100	1			T3	4		T14	61		T15	6
valid_sources[0x57]	12830	1			T3	13		T14	34		T15	6
valid_sources[0x58]	5510	1			T3	2		T14	55		T15	3
valid_sources[0x59]	5595	1			T3	8		T14	43		T15	15
valid_sources[0x5a]	5505	1			T3	15		T4	5		T14	21
valid_sources[0x5b]	5415	1			T2	1		T3	27		T14	51
valid_sources[0x5c]	5775	1			T2	2		T3	6		T4	8
valid_sources[0x5d]	5452	1			T3	10		T4	1		T14	31
valid_sources[0x5e]	5626	1			T3	18		T14	53		T15	4
valid_sources[0x5f]	6702	1			T3	21		T14	30		T15	7
valid_sources[0x60]	7728	1			T2	1		T3	65		T14	27
valid_sources[0x61]	5813	1			T3	11		T4	3		T14	39
valid_sources[0x62]	7891	1			T14	35		T15	6		T6	1
valid_sources[0x63]	5582	1			T3	25		T14	43		T15	11
valid_sources[0x64]	5341	1			T3	11		T14	22		T15	5
valid_sources[0x65]	6660	1			T3	16		T14	46		T15	3
valid_sources[0x66]	5954	1			T3	9		T12	3		T4	41
valid_sources[0x67]	5508	1			T3	18		T14	45		T15	7
valid_sources[0x68]	6851	1			T3	1		T14	30		T15	19
valid_sources[0x69]	6125	1			T3	7		T14	43		T15	9
valid_sources[0x6a]	5630	1			T3	15		T14	83		T15	13
valid_sources[0x6b]	5512	1			T3	38		T14	46		T15	4
valid_sources[0x6c]	5798	1			T3	22		T14	70		T15	11
valid_sources[0x6d]	5652	1			T3	1		T14	48		T15	11
valid_sources[0x6e]	12090	1			T3	21		T14	51		T15	15
valid_sources[0x6f]	5420	1			T3	8		T4	1		T14	53
valid_sources[0x70]	5656	1			T3	24		T14	32		T15	5
valid_sources[0x71]	5584	1			T3	8		T14	66		T15	6
valid_sources[0x72]	5330	1			T2	4		T3	9		T4	2
valid_sources[0x73]	7792	1			T3	16		T4	2		T14	52
valid_sources[0x74]	5793	1			T3	34		T14	64		T15	8
valid_sources[0x75]	5632	1			T3	12		T4	12		T14	31
valid_sources[0x76]	7366	1			T3	9		T14	58		T15	2
valid_sources[0x77]	5285	1			T3	13		T4	13		T14	37
valid_sources[0x78]	6622	1			T3	3		T14	41		T15	8
valid_sources[0x79]	5455	1			T3	37		T14	17		T6	2
valid_sources[0x7a]	10746	1			T3	4		T14	52		T15	5
valid_sources[0x7b]	27790	1			T3	3		T14	27		T15	4
valid_sources[0x7c]	5353	1			T3	7		T14	50		T15	4
valid_sources[0x7d]	7749	1			T2	6		T3	1		T14	35
valid_sources[0x7e]	5475	1			T3	15		T4	4		T14	20
valid_sources[0x7f]	5474	1			T3	12		T14	44		T15	3
valid_sources[0x80]	6856	1			T3	21		T14	42		T15	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

746721

1

T2

30

T3

2076

T12

2

values[0x0]

all_enables

biggest_size

124409

1

T1

5

T2

11

T3

32

values[0x1]

all_enables

biggest_size

124302

1

T1

1

T2

15

T3

36