Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	59328125	13286	0	0
claim_transition_if_regwen_rd_A	59328125	1317	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59328125	13286	0	0
T56	30821	0	0	0
T93	149462	6	0	0
T94	0	11	0	0
T95	0	6	0	0
T99	0	20	0	0
T117	0	3	0	0
T152	0	1	0	0
T156	0	1	0	0
T157	0	11	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	34859	0	0	0
T161	37337	0	0	0
T162	3430	0	0	0
T163	30782	0	0	0
T164	30017	0	0	0
T165	4858	0	0	0
T166	33056	0	0	0
T167	46686	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59328125	1317	0	0
T86	20592	0	0	0
T119	0	28	0	0
T134	0	3	0	0
T135	0	1	0	0
T152	381561	16	0	0
T159	0	1	0	0
T168	0	2	0	0
T169	0	12	0	0
T170	0	4	0	0
T171	0	14	0	0
T172	0	242	0	0
T173	133964	0	0	0
T174	192939	0	0	0
T175	29508	0	0	0
T176	47608	0	0	0
T177	717	0	0	0
T178	1569	0	0	0
T179	32399	0	0	0
T180	21062	0	0	0