Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.64	100.00	55.56	75.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	75.00			75.00
tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	75.00			75.00
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.00			75.00				gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.00			75.00				u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
clk1_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	41309174	41307542	0	0
selKnown1	57486936	57485304	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	41309174	41307542	0	0
T2	5	4	0	0
T3	10	9	0	0
T4	15	14	0	0
T5	50295	50293	0	0
T6	44472	44470	0	0
T7	64820	64818	0	0
T8	0	45347	0	0
T10	62677	62694	0	0
T11	150295	150347	0	0
T12	1	0	0	0
T13	60	58	0	0
T14	7	5	0	0
T15	53	51	0	0
T17	1	60	0	0
T26	0	59879	0	0
T27	0	6238	0	0
T28	0	15859	0	0
T29	0	150448	0	0
T30	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	57486936	57485304	0	0
T1	1280	1279	0	0
T2	2291	2290	0	0
T3	10124	10123	0	0
T4	9117	9116	0	0
T5	31770	31769	0	0
T6	29579	29578	0	0
T7	5	4	0	0
T8	0	2	0	0
T9	0	3	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	835	834	0	0
T13	28249	28248	0	0
T14	23082	23081	0	0
T15	30836	30835	0	0
T17	1	0	0	0
T18	1	0	0	0
T22	1	0	0	0
T26	1	0	0	0
T30	1	0	0	0
T31	0	3	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T36	0	5	0	0
T37	0	1	0	0
T38	1	0	0	0
T39	1	0	0	0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
clk1_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T5,T10,T11	Yes	T5,T6,T7	INPUT
clk1_i	Yes	Yes	T6,T7,T8	Yes	T7,T8,T9	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T5,T10,T11	Yes	T5,T6,T7	OUTPUT

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	41266838	41266022	0	0
selKnown1	57485993	57485177	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	41266838	41266022	0	0
T5	50275	50274	0	0
T6	44471	44470	0	0
T7	64819	64818	0	0
T8	0	45347	0	0
T10	62677	62676	0	0
T11	150295	150294	0	0
T13	1	0	0	0
T14	1	0	0	0
T15	1	0	0	0
T17	1	0	0	0
T26	0	59879	0	0
T27	0	6238	0	0
T28	0	15859	0	0
T29	0	150448	0	0
T30	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	57485993	57485177	0	0
T1	1280	1279	0	0
T2	2291	2290	0	0
T3	10124	10123	0	0
T4	9117	9116	0	0
T5	31770	31769	0	0
T6	29579	29578	0	0
T12	835	834	0	0
T13	28249	28248	0	0
T14	23082	23081	0	0
T15	30836	30835	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	42336	41520	0	0
selKnown1	943	127	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	42336	41520	0	0
T2	5	4	0	0
T3	10	9	0	0
T4	15	14	0	0
T5	20	19	0	0
T6	1	0	0	0
T7	1	0	0	0
T10	0	18	0	0
T11	0	53	0	0
T12	1	0	0	0
T13	59	58	0	0
T14	6	5	0	0
T15	52	51	0	0
T17	0	60	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	943	127	0	0
T7	5	4	0	0
T8	0	2	0	0
T9	0	3	0	0
T10	1	0	0	0
T11	1	0	0	0
T17	1	0	0	0
T18	1	0	0	0
T22	1	0	0	0
T26	1	0	0	0
T30	1	0	0	0
T31	0	3	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	4	0	0
T36	0	5	0	0
T37	0	1	0	0
T38	1	0	0	0
T39	1	0	0	0