Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	738208	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

917785

1

T1

6

T2

352

T3

368

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1374453	1			T1	3		T2	578		T3	325
values[0x0]	140644	1			T1	4		T2	31		T3	118
values[0x1]	140896	1			T1	4		T2	39		T3	114

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	583946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1072047

1

T1

7

T2

416

T3

403

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5683	1			T2	2		T4	1		T13	2
valid_sources[0x01]	5426	1			T2	4		T3	5		T4	4
valid_sources[0x02]	5618	1			T2	3		T4	2		T13	1
valid_sources[0x03]	7941	1			T2	6		T4	3		T13	5
valid_sources[0x04]	5866	1			T2	3		T3	2		T4	1
valid_sources[0x05]	6707	1			T1	1		T2	2		T3	1
valid_sources[0x06]	5601	1			T2	3		T3	2		T4	1
valid_sources[0x07]	5405	1			T2	4		T4	2		T13	9
valid_sources[0x08]	5965	1			T2	5		T4	1		T12	2
valid_sources[0x09]	5705	1			T2	2		T3	2		T4	3
valid_sources[0x0a]	7301	1			T1	1		T2	3		T4	3
valid_sources[0x0b]	7144	1			T2	3		T3	4		T4	3
valid_sources[0x0c]	5433	1			T2	2		T3	1		T4	3
valid_sources[0x0d]	6759	1			T2	2		T3	7		T4	3
valid_sources[0x0e]	5687	1			T2	2		T3	3		T4	3
valid_sources[0x0f]	5419	1			T2	5		T4	1		T12	1
valid_sources[0x10]	5219	1			T2	3		T4	2		T12	1
valid_sources[0x11]	5294	1			T2	2		T3	8		T13	1
valid_sources[0x12]	5495	1			T2	2		T4	2		T12	1
valid_sources[0x13]	6907	1			T4	7		T13	4		T15	33
valid_sources[0x14]	5619	1			T2	1		T3	1		T4	4
valid_sources[0x15]	7293	1			T2	4		T12	3		T13	5
valid_sources[0x16]	5560	1			T2	3		T3	3		T4	2
valid_sources[0x17]	5505	1			T2	1		T4	6		T12	5
valid_sources[0x18]	6363	1			T2	3		T12	3		T13	2
valid_sources[0x19]	5769	1			T2	4		T4	2		T12	1
valid_sources[0x1a]	9607	1			T2	6		T3	2		T4	3
valid_sources[0x1b]	7248	1			T2	2		T3	3		T12	1
valid_sources[0x1c]	9752	1			T2	4		T3	5		T4	1
valid_sources[0x1d]	5546	1			T2	1		T4	7		T12	2
valid_sources[0x1e]	5424	1			T2	2		T3	6		T4	4
valid_sources[0x1f]	5921	1			T2	6		T13	2		T15	31
valid_sources[0x20]	5505	1			T2	3		T3	7		T12	1
valid_sources[0x21]	5547	1			T3	1		T4	4		T13	3
valid_sources[0x22]	5917	1			T13	1		T15	46		T16	18
valid_sources[0x23]	5542	1			T2	1		T3	1		T4	1
valid_sources[0x24]	5429	1			T2	1		T3	6		T4	3
valid_sources[0x25]	6471	1			T2	1		T4	3		T13	7
valid_sources[0x26]	5558	1			T2	3		T3	3		T4	3
valid_sources[0x27]	6530	1			T3	1		T13	2		T15	43
valid_sources[0x28]	7345	1			T2	2		T3	6		T13	5
valid_sources[0x29]	5776	1			T2	2		T4	2		T13	10
valid_sources[0x2a]	5591	1			T1	1		T2	3		T3	7
valid_sources[0x2b]	5342	1			T2	6		T4	2		T13	5
valid_sources[0x2c]	7316	1			T2	3		T4	2		T12	8
valid_sources[0x2d]	5763	1			T2	1		T3	3		T4	1
valid_sources[0x2e]	7489	1			T4	2		T13	1		T15	31
valid_sources[0x2f]	5811	1			T2	3		T3	3		T4	3
valid_sources[0x30]	26046	1			T2	2		T3	1		T4	4
valid_sources[0x31]	5623	1			T2	2		T4	2		T12	3
valid_sources[0x32]	5770	1			T2	1		T3	6		T4	1
valid_sources[0x33]	5675	1			T2	4		T4	4		T12	1
valid_sources[0x34]	5367	1			T2	4		T4	8		T13	1
valid_sources[0x35]	5470	1			T2	5		T3	1		T4	5
valid_sources[0x36]	6725	1			T2	1		T4	1		T12	3
valid_sources[0x37]	5868	1			T2	4		T4	6		T12	1
valid_sources[0x38]	5191	1			T4	2		T12	1		T13	2
valid_sources[0x39]	8135	1			T4	1		T13	9		T15	37
valid_sources[0x3a]	8714	1			T2	2		T3	15		T4	3
valid_sources[0x3b]	5674	1			T2	1		T3	4		T13	4
valid_sources[0x3c]	5326	1			T2	4		T4	4		T13	2
valid_sources[0x3d]	5386	1			T2	5		T3	9		T4	3
valid_sources[0x3e]	9671	1			T2	1		T4	1		T13	5
valid_sources[0x3f]	10328	1			T2	2		T3	7		T4	1
valid_sources[0x40]	5554	1			T2	2		T3	1		T4	3
valid_sources[0x41]	5593	1			T2	2		T3	3		T4	2
valid_sources[0x42]	6694	1			T2	2		T3	3		T4	2
valid_sources[0x43]	7061	1			T2	5		T3	7		T4	1
valid_sources[0x44]	5506	1			T2	3		T3	5		T4	3
valid_sources[0x45]	5728	1			T2	1		T4	5		T13	7
valid_sources[0x46]	5904	1			T2	2		T12	6		T13	7
valid_sources[0x47]	11792	1			T2	3		T4	5		T12	5
valid_sources[0x48]	5862	1			T3	1		T4	2		T13	7
valid_sources[0x49]	5581	1			T2	2		T3	3		T12	2
valid_sources[0x4a]	6753	1			T2	2		T4	3		T13	3
valid_sources[0x4b]	6081	1			T2	1		T3	5		T4	2
valid_sources[0x4c]	5779	1			T4	2		T13	1		T15	35
valid_sources[0x4d]	5810	1			T3	4		T4	1		T13	1
valid_sources[0x4e]	5985	1			T2	1		T3	1		T4	3
valid_sources[0x4f]	5560	1			T2	2		T3	1		T4	5
valid_sources[0x50]	6451	1			T2	3		T4	4		T15	43
valid_sources[0x51]	7366	1			T2	2		T13	7		T15	42
valid_sources[0x52]	5627	1			T2	3		T3	5		T4	2
valid_sources[0x53]	8963	1			T2	1		T3	4		T4	2
valid_sources[0x54]	5864	1			T2	1		T3	5		T4	3
valid_sources[0x55]	13627	1			T2	3		T3	5		T4	3
valid_sources[0x56]	5609	1			T2	4		T3	4		T4	10
valid_sources[0x57]	5345	1			T2	4		T4	7		T12	5
valid_sources[0x58]	5490	1			T2	3		T3	5		T4	4
valid_sources[0x59]	5777	1			T2	2		T3	3		T4	2
valid_sources[0x5a]	15932	1			T2	3		T3	2		T4	2
valid_sources[0x5b]	7275	1			T2	5		T4	4		T13	1
valid_sources[0x5c]	7307	1			T2	4		T3	1		T4	2
valid_sources[0x5d]	7527	1			T2	2		T3	5		T4	2
valid_sources[0x5e]	5270	1			T2	2		T3	1		T4	3
valid_sources[0x5f]	7735	1			T2	3		T4	4		T12	1
valid_sources[0x60]	5475	1			T2	1		T3	5		T4	6
valid_sources[0x61]	5391	1			T2	2		T4	5		T12	1
valid_sources[0x62]	5573	1			T2	1		T3	2		T4	2
valid_sources[0x63]	6765	1			T1	1		T2	4		T3	7
valid_sources[0x64]	6805	1			T2	4		T4	1		T12	1
valid_sources[0x65]	5608	1			T2	1		T4	1		T15	35
valid_sources[0x66]	5722	1			T2	3		T15	36		T7	2
valid_sources[0x67]	5561	1			T2	4		T4	4		T13	8
valid_sources[0x68]	5754	1			T2	5		T4	2		T12	1
valid_sources[0x69]	5834	1			T2	2		T4	1		T13	8
valid_sources[0x6a]	5318	1			T2	2		T4	5		T13	3
valid_sources[0x6b]	7453	1			T2	1		T3	5		T4	3
valid_sources[0x6c]	5722	1			T2	4		T4	1		T13	13
valid_sources[0x6d]	6268	1			T2	5		T3	2		T4	3
valid_sources[0x6e]	6675	1			T2	1		T3	4		T4	4
valid_sources[0x6f]	5904	1			T2	4		T4	4		T13	4
valid_sources[0x70]	5532	1			T3	3		T4	2		T12	2
valid_sources[0x71]	5449	1			T3	9		T4	1		T12	3
valid_sources[0x72]	6078	1			T2	4		T4	3		T13	4
valid_sources[0x73]	8779	1			T2	2		T3	4		T4	3
valid_sources[0x74]	5453	1			T2	2		T3	3		T4	4
valid_sources[0x75]	5338	1			T2	2		T3	9		T4	5
valid_sources[0x76]	7568	1			T2	3		T3	2		T4	1
valid_sources[0x77]	5503	1			T2	1		T3	13		T4	2
valid_sources[0x78]	5636	1			T2	1		T3	1		T4	4
valid_sources[0x79]	5903	1			T2	1		T4	1		T12	2
valid_sources[0x7a]	5812	1			T2	3		T4	3		T13	2
valid_sources[0x7b]	5545	1			T2	3		T4	2		T13	4
valid_sources[0x7c]	5697	1			T2	3		T3	1		T4	1
valid_sources[0x7d]	5457	1			T2	5		T3	4		T12	2
valid_sources[0x7e]	5344	1			T2	4		T3	1		T4	1
valid_sources[0x7f]	5554	1			T2	1		T4	5		T13	2
valid_sources[0x80]	6242	1			T2	2		T3	4		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

675625

1

T2

296

T3

160

T4

137

values[0x0]

all_enables

biggest_size

121769

1

T1

3

T2

25

T3

108

values[0x1]

all_enables

biggest_size

120391

1

T1

3

T2

31

T3

100