Unified Coverage Report :: Module :: dmi_jtag

Module : dmi_jtag

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.78			74.78

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag	74.78			74.78

---

Module Instance : tb.dut.u_dmi_jtag

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.78			74.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.46			80.46

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_dmi_cdc	81.38			81.38
i_dmi_jtag_tap	83.87			83.87

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : dmi_jtag

	Total	Covered	Percent
Totals	20	17	85.00
Total Bits	230	172	74.78
Total Bits 0->1	115	86	74.78
Total Bits 1->0	115	86	74.78

Ports	20	17	85.00
Port Bits	230	172	74.78
Port Bits 0->1	115	86	74.78
Port Bits 1->0	115	86	74.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
testmode_i	No	No		No		INPUT
test_rst_ni	Yes	Yes	T7,T8,T9	Yes	T7,T9,T10	INPUT
dmi_rst_no	Yes	Yes	T5,T6,T11	Yes	T5,T6,T7	OUTPUT
dmi_req_o.data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
dmi_req_o.op[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
dmi_req_o.addr[5:0]	Yes	Yes	T5,T6,*T7	Yes	T5,T6,T7	OUTPUT
dmi_req_o.addr[31:6]	No	No		No		OUTPUT
dmi_req_valid_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
dmi_req_ready_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
dmi_resp_i.resp[1:0]	No	No		No		INPUT
dmi_resp_i.data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
dmi_resp_ready_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
dmi_resp_valid_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tck_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tms_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
trst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
td_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
td_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tdo_oe_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

*Tests covering at least one bit in the range