Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	59131515	13710	0	0
claim_transition_if_regwen_rd_A	59131515	1431	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59131515	13710	0	0
T26	31362	0	0	0
T58	31638	0	0	0
T60	21400	0	0	0
T65	348592	4	0	0
T85	5711	0	0	0
T97	0	12	0	0
T98	0	11	0	0
T101	54380	0	0	0
T145	0	5	0	0
T146	0	2	0	0
T147	0	10	0	0
T148	0	8	0	0
T149	0	19	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	51268	0	0	0
T153	6125	0	0	0
T154	7210	0	0	0
T155	36470	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59131515	1431	0	0
T115	0	72	0	0
T143	0	1	0	0
T145	581855	8	0	0
T150	0	8	0	0
T151	0	3	0	0
T156	0	110	0	0
T157	0	267	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	766	0	0	0
T162	1673	0	0	0
T163	74282	0	0	0
T164	1279	0	0	0
T165	62195	0	0	0
T166	21306	0	0	0
T167	21905	0	0	0
T168	100987	0	0	0
T169	20777	0	0	0