Unified Coverage Report :: Module :: prim_subreg_ext

Module : prim_subreg_ext

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_hw_revision0_product_id	33.33	33.33
tb.dut.u_reg.u_hw_revision0_silicon_creator_id	33.33	33.33
tb.dut.u_reg.u_hw_revision1_revision_id	33.33	33.33
tb.dut.u_reg.u_hw_revision1_reserved	33.33	33.33
tb.dut.u_reg_tap.u_hw_revision0_product_id	33.33	33.33
tb.dut.u_reg_tap.u_hw_revision0_silicon_creator_id	33.33	33.33
tb.dut.u_reg_tap.u_hw_revision1_revision_id	33.33	33.33
tb.dut.u_reg_tap.u_hw_revision1_reserved	33.33	33.33
tb.dut.u_reg.u_lc_id_state	66.67	66.67
tb.dut.u_reg.u_alert_test_fatal_prog_error	100.00	100.00
tb.dut.u_reg.u_alert_test_fatal_state_error	100.00	100.00
tb.dut.u_reg.u_alert_test_fatal_bus_integ_error	100.00	100.00
tb.dut.u_reg.u_status_initialized	100.00	100.00
tb.dut.u_reg.u_status_ready	100.00	100.00
tb.dut.u_reg.u_status_ext_clock_switched	100.00	100.00
tb.dut.u_reg.u_status_transition_successful	100.00	100.00
tb.dut.u_reg.u_status_transition_count_error	100.00	100.00
tb.dut.u_reg.u_status_transition_error	100.00	100.00
tb.dut.u_reg.u_status_token_error	100.00	100.00
tb.dut.u_reg.u_status_flash_rma_error	100.00	100.00
tb.dut.u_reg.u_status_otp_error	100.00	100.00
tb.dut.u_reg.u_status_state_error	100.00	100.00
tb.dut.u_reg.u_status_bus_integ_error	100.00	100.00
tb.dut.u_reg.u_status_otp_partition_error	100.00	100.00
tb.dut.u_reg.u_claim_transition_if	100.00	100.00
tb.dut.u_reg.u_transition_regwen	100.00	100.00
tb.dut.u_reg.u_transition_cmd	100.00	100.00
tb.dut.u_reg.u_transition_ctrl_ext_clock_en	100.00	100.00
tb.dut.u_reg.u_transition_ctrl_volatile_raw_unlock	100.00	100.00
tb.dut.u_reg.u_transition_token_0	100.00	100.00
tb.dut.u_reg.u_transition_token_1	100.00	100.00
tb.dut.u_reg.u_transition_token_2	100.00	100.00
tb.dut.u_reg.u_transition_token_3	100.00	100.00
tb.dut.u_reg.u_transition_target	100.00	100.00
tb.dut.u_reg.u_otp_vendor_test_ctrl	100.00	100.00
tb.dut.u_reg.u_otp_vendor_test_status	100.00	100.00
tb.dut.u_reg.u_lc_state	100.00	100.00
tb.dut.u_reg.u_lc_transition_cnt	100.00	100.00
tb.dut.u_reg.u_device_id_0	100.00	100.00
tb.dut.u_reg.u_device_id_1	100.00	100.00
tb.dut.u_reg.u_device_id_2	100.00	100.00
tb.dut.u_reg.u_device_id_3	100.00	100.00
tb.dut.u_reg.u_device_id_4	100.00	100.00
tb.dut.u_reg.u_device_id_5	100.00	100.00
tb.dut.u_reg.u_device_id_6	100.00	100.00
tb.dut.u_reg.u_device_id_7	100.00	100.00
tb.dut.u_reg.u_manuf_state_0	100.00	100.00
tb.dut.u_reg.u_manuf_state_1	100.00	100.00
tb.dut.u_reg.u_manuf_state_2	100.00	100.00
tb.dut.u_reg.u_manuf_state_3	100.00	100.00
tb.dut.u_reg.u_manuf_state_4	100.00	100.00
tb.dut.u_reg.u_manuf_state_5	100.00	100.00
tb.dut.u_reg.u_manuf_state_6	100.00	100.00
tb.dut.u_reg.u_manuf_state_7	100.00	100.00
tb.dut.u_reg_tap.u_alert_test_fatal_prog_error	100.00	100.00
tb.dut.u_reg_tap.u_alert_test_fatal_state_error	100.00	100.00
tb.dut.u_reg_tap.u_alert_test_fatal_bus_integ_error	100.00	100.00
tb.dut.u_reg_tap.u_status_initialized	100.00	100.00
tb.dut.u_reg_tap.u_status_ready	100.00	100.00
tb.dut.u_reg_tap.u_status_ext_clock_switched	100.00	100.00
tb.dut.u_reg_tap.u_status_transition_successful	100.00	100.00
tb.dut.u_reg_tap.u_status_transition_count_error	100.00	100.00
tb.dut.u_reg_tap.u_status_transition_error	100.00	100.00
tb.dut.u_reg_tap.u_status_token_error	100.00	100.00
tb.dut.u_reg_tap.u_status_flash_rma_error	100.00	100.00
tb.dut.u_reg_tap.u_status_otp_error	100.00	100.00
tb.dut.u_reg_tap.u_status_state_error	100.00	100.00
tb.dut.u_reg_tap.u_status_bus_integ_error	100.00	100.00
tb.dut.u_reg_tap.u_status_otp_partition_error	100.00	100.00
tb.dut.u_reg_tap.u_claim_transition_if	100.00	100.00
tb.dut.u_reg_tap.u_transition_regwen	100.00	100.00
tb.dut.u_reg_tap.u_transition_cmd	100.00	100.00
tb.dut.u_reg_tap.u_transition_ctrl_ext_clock_en	100.00	100.00
tb.dut.u_reg_tap.u_transition_ctrl_volatile_raw_unlock	100.00	100.00
tb.dut.u_reg_tap.u_transition_token_0	100.00	100.00
tb.dut.u_reg_tap.u_transition_token_1	100.00	100.00
tb.dut.u_reg_tap.u_transition_token_2	100.00	100.00
tb.dut.u_reg_tap.u_transition_token_3	100.00	100.00
tb.dut.u_reg_tap.u_transition_target	100.00	100.00
tb.dut.u_reg_tap.u_otp_vendor_test_ctrl	100.00	100.00
tb.dut.u_reg_tap.u_otp_vendor_test_status	100.00	100.00
tb.dut.u_reg_tap.u_lc_state	100.00	100.00
tb.dut.u_reg_tap.u_lc_transition_cnt	100.00	100.00
tb.dut.u_reg_tap.u_lc_id_state	100.00	100.00
tb.dut.u_reg_tap.u_device_id_0	100.00	100.00
tb.dut.u_reg_tap.u_device_id_1	100.00	100.00
tb.dut.u_reg_tap.u_device_id_2	100.00	100.00
tb.dut.u_reg_tap.u_device_id_3	100.00	100.00
tb.dut.u_reg_tap.u_device_id_4	100.00	100.00
tb.dut.u_reg_tap.u_device_id_5	100.00	100.00
tb.dut.u_reg_tap.u_device_id_6	100.00	100.00
tb.dut.u_reg_tap.u_device_id_7	100.00	100.00
tb.dut.u_reg_tap.u_manuf_state_0	100.00	100.00
tb.dut.u_reg_tap.u_manuf_state_1	100.00	100.00
tb.dut.u_reg_tap.u_manuf_state_2	100.00	100.00
tb.dut.u_reg_tap.u_manuf_state_3	100.00	100.00
tb.dut.u_reg_tap.u_manuf_state_4	100.00	100.00
tb.dut.u_reg_tap.u_manuf_state_5	100.00	100.00
tb.dut.u_reg_tap.u_manuf_state_6	100.00	100.00
tb.dut.u_reg_tap.u_manuf_state_7	100.00	100.00

---

Module Instance : tb.dut.u_reg.u_hw_revision0_product_id

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_hw_revision0_silicon_creator_id

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_hw_revision1_revision_id

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_hw_revision1_reserved

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_hw_revision0_product_id

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_hw_revision0_silicon_creator_id

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_hw_revision1_revision_id

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_hw_revision1_reserved

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
33.33	33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_lc_id_state

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_alert_test_fatal_prog_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_alert_test_fatal_state_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_alert_test_fatal_bus_integ_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_initialized

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_ready

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_ext_clock_switched

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_transition_successful

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_transition_count_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_transition_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_token_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_flash_rma_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_otp_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_state_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_bus_integ_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_status_otp_partition_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_claim_transition_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_transition_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_transition_cmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_transition_ctrl_ext_clock_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_transition_ctrl_volatile_raw_unlock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_transition_token_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_transition_token_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_transition_token_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_transition_token_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_transition_target

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_otp_vendor_test_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_otp_vendor_test_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_lc_state

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_lc_transition_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_device_id_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_device_id_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_device_id_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_device_id_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_device_id_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_device_id_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_device_id_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_device_id_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_manuf_state_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_manuf_state_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_manuf_state_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_manuf_state_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_manuf_state_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_manuf_state_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_manuf_state_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_manuf_state_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.77	100.00	99.07			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_alert_test_fatal_prog_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_alert_test_fatal_state_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_alert_test_fatal_bus_integ_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_initialized

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_ready

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_ext_clock_switched

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_transition_successful

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_transition_count_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_transition_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_token_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_flash_rma_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_otp_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_state_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_bus_integ_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_status_otp_partition_error

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_claim_transition_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_transition_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_transition_cmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_transition_ctrl_ext_clock_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_transition_ctrl_volatile_raw_unlock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_transition_token_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_transition_token_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_transition_token_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_transition_token_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_transition_target

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_otp_vendor_test_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_otp_vendor_test_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_lc_state

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_lc_transition_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_lc_id_state

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_device_id_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_device_id_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_device_id_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_device_id_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_device_id_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_device_id_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_device_id_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_device_id_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_manuf_state_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_manuf_state_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_manuf_state_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_manuf_state_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_manuf_state_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_manuf_state_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_manuf_state_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_manuf_state_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.73	100.00	98.92			100.00	100.00	u_reg_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_subreg_ext

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_hw_revision0_product_id

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_hw_revision0_silicon_creator_id

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_hw_revision1_revision_id

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_hw_revision1_reserved

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg_tap.u_hw_revision0_product_id

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_hw_revision0_silicon_creator_id

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_hw_revision1_revision_id

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_hw_revision1_reserved

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_lc_id_state

	Line No.	Total	Covered	Percent
TOTAL		3	2	66.67
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_alert_test_fatal_prog_error

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T38 T95 T96 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_alert_test_fatal_state_error

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T38 T95 T96 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_alert_test_fatal_bus_integ_error

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T38 T95 T96 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_status_initialized

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_ready

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_ext_clock_switched

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_transition_successful

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_transition_count_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_transition_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_token_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_flash_rma_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_otp_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_state_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_bus_integ_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_status_otp_partition_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg.u_claim_transition_if

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T3 T4 T12 

Line Coverage for Instance : tb.dut.u_reg.u_transition_regwen

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T14 T15 T7 

Line Coverage for Instance : tb.dut.u_reg.u_transition_cmd

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg.u_transition_ctrl_ext_clock_en

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T15 
30         1/1            assign qre = re;
           Tests:       T1 T15 T7 

Line Coverage for Instance : tb.dut.u_reg.u_transition_ctrl_volatile_raw_unlock

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T15 
30         1/1            assign qre = re;
           Tests:       T1 T15 T7 

Line Coverage for Instance : tb.dut.u_reg.u_transition_token_0

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T15 T7 T8 

Line Coverage for Instance : tb.dut.u_reg.u_transition_token_1

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T15 T7 T8 

Line Coverage for Instance : tb.dut.u_reg.u_transition_token_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T15 T7 T8 

Line Coverage for Instance : tb.dut.u_reg.u_transition_token_3

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T15 T7 T8 

Line Coverage for Instance : tb.dut.u_reg.u_transition_target

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T15 T7 T8 

Line Coverage for Instance : tb.dut.u_reg.u_otp_vendor_test_ctrl

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T2 T3 T12 
30         1/1            assign qre = re;
           Tests:       T15 T7 T8 

Line Coverage for Instance : tb.dut.u_reg.u_otp_vendor_test_status

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_lc_state

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_lc_transition_cnt

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_device_id_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_device_id_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_device_id_2

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_device_id_3

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_device_id_4

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_device_id_5

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_device_id_6

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_device_id_7

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_manuf_state_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_manuf_state_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_manuf_state_2

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_manuf_state_3

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_manuf_state_4

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_manuf_state_5

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_manuf_state_6

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg.u_manuf_state_7

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T2 T3 T4 

Line Coverage for Instance : tb.dut.u_reg_tap.u_alert_test_fatal_prog_error

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_tap.u_alert_test_fatal_state_error

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_tap.u_alert_test_fatal_bus_integ_error

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_initialized

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_ready

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_ext_clock_switched

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_transition_successful

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_transition_count_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_transition_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_token_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_flash_rma_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_otp_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_state_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_bus_integ_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_status_otp_partition_error

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_claim_transition_if

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_transition_regwen

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_transition_cmd

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.u_reg_tap.u_transition_ctrl_ext_clock_en

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_transition_ctrl_volatile_raw_unlock

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_transition_token_0

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_transition_token_1

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_transition_token_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_transition_token_3

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_transition_target

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_otp_vendor_test_ctrl

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T5 T6 T7 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_otp_vendor_test_status

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_lc_state

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_lc_transition_cnt

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_lc_id_state

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_device_id_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_device_id_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_device_id_2

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_device_id_3

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_device_id_4

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_device_id_5

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_device_id_6

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_device_id_7

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_manuf_state_0

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_manuf_state_1

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_manuf_state_2

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_manuf_state_3

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_manuf_state_4

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_manuf_state_5

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_manuf_state_6

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_tap.u_manuf_state_7

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	0	0
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         unreachable    assign q = wd;
29         unreachable    assign qe = we;
30         1/1            assign qre = re;
           Tests:       T1 T2 T3