| T580 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.2939208628 |
|
|
Sep 18 12:44:08 PM UTC 24 |
Sep 18 12:44:39 PM UTC 24 |
1090538836 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.2634390532 |
|
|
Sep 18 12:44:39 PM UTC 24 |
Sep 18 12:44:41 PM UTC 24 |
38710119 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.4185330915 |
|
|
Sep 18 12:44:29 PM UTC 24 |
Sep 18 12:44:42 PM UTC 24 |
1128593838 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.383918713 |
|
|
Sep 18 12:44:29 PM UTC 24 |
Sep 18 12:44:42 PM UTC 24 |
600007870 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.3012063978 |
|
|
Sep 18 12:44:28 PM UTC 24 |
Sep 18 12:44:42 PM UTC 24 |
713198651 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.2232875739 |
|
|
Sep 18 12:44:17 PM UTC 24 |
Sep 18 12:44:42 PM UTC 24 |
1389513300 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.1252115967 |
|
|
Sep 18 12:44:39 PM UTC 24 |
Sep 18 12:44:42 PM UTC 24 |
25444106 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.4161035649 |
|
|
Sep 18 12:39:19 PM UTC 24 |
Sep 18 12:44:42 PM UTC 24 |
102981829774 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1500767726 |
|
|
Sep 18 12:44:40 PM UTC 24 |
Sep 18 12:44:42 PM UTC 24 |
12117508 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.2243221747 |
|
|
Sep 18 12:44:21 PM UTC 24 |
Sep 18 12:44:42 PM UTC 24 |
576726379 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.3871829757 |
|
|
Sep 18 12:44:29 PM UTC 24 |
Sep 18 12:44:44 PM UTC 24 |
1517447920 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.439810550 |
|
|
Sep 18 12:44:36 PM UTC 24 |
Sep 18 12:44:44 PM UTC 24 |
1200982050 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1838074396 |
|
|
Sep 18 12:43:19 PM UTC 24 |
Sep 18 12:44:44 PM UTC 24 |
6866321696 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.2451653839 |
|
|
Sep 18 12:44:34 PM UTC 24 |
Sep 18 12:44:44 PM UTC 24 |
718036811 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.2761331275 |
|
|
Sep 18 12:44:28 PM UTC 24 |
Sep 18 12:44:45 PM UTC 24 |
1237171466 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.2645136583 |
|
|
Sep 18 12:44:35 PM UTC 24 |
Sep 18 12:44:45 PM UTC 24 |
1077207531 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.3584811877 |
|
|
Sep 18 12:44:29 PM UTC 24 |
Sep 18 12:44:45 PM UTC 24 |
2592961448 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.961632988 |
|
|
Sep 18 12:44:35 PM UTC 24 |
Sep 18 12:44:47 PM UTC 24 |
3869819059 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.355049708 |
|
|
Sep 18 12:45:08 PM UTC 24 |
Sep 18 12:45:13 PM UTC 24 |
367538511 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.1022054096 |
|
|
Sep 18 12:44:36 PM UTC 24 |
Sep 18 12:44:48 PM UTC 24 |
3302871580 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.656066715 |
|
|
Sep 18 12:44:42 PM UTC 24 |
Sep 18 12:44:48 PM UTC 24 |
62514422 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.422130019 |
|
|
Sep 18 12:44:46 PM UTC 24 |
Sep 18 12:44:48 PM UTC 24 |
50178816 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1408022816 |
|
|
Sep 18 12:44:46 PM UTC 24 |
Sep 18 12:44:49 PM UTC 24 |
14814106 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.1812051816 |
|
|
Sep 18 12:44:46 PM UTC 24 |
Sep 18 12:44:50 PM UTC 24 |
189021303 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.2856125077 |
|
|
Sep 18 12:44:42 PM UTC 24 |
Sep 18 12:44:51 PM UTC 24 |
1165914336 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.390722894 |
|
|
Sep 18 12:44:37 PM UTC 24 |
Sep 18 12:44:51 PM UTC 24 |
508546391 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.4066331769 |
|
|
Sep 18 12:44:46 PM UTC 24 |
Sep 18 12:44:52 PM UTC 24 |
171015183 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.1424244447 |
|
|
Sep 18 12:43:24 PM UTC 24 |
Sep 18 12:44:52 PM UTC 24 |
40753006853 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.3859622810 |
|
|
Sep 18 12:44:42 PM UTC 24 |
Sep 18 12:44:53 PM UTC 24 |
47695013 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.1278603317 |
|
|
Sep 18 12:44:44 PM UTC 24 |
Sep 18 12:44:53 PM UTC 24 |
223251422 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.764423928 |
|
|
Sep 18 12:44:37 PM UTC 24 |
Sep 18 12:44:54 PM UTC 24 |
1645269345 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.984849781 |
|
|
Sep 18 12:44:26 PM UTC 24 |
Sep 18 12:44:55 PM UTC 24 |
746932619 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.3461592341 |
|
|
Sep 18 12:44:53 PM UTC 24 |
Sep 18 12:44:56 PM UTC 24 |
41691739 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2551485763 |
|
|
Sep 18 12:44:53 PM UTC 24 |
Sep 18 12:44:56 PM UTC 24 |
14235308 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.2742239795 |
|
|
Sep 18 12:44:46 PM UTC 24 |
Sep 18 12:44:56 PM UTC 24 |
189723503 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.3801249903 |
|
|
Sep 18 12:44:53 PM UTC 24 |
Sep 18 12:44:57 PM UTC 24 |
53049962 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2650525963 |
|
|
Sep 18 12:44:49 PM UTC 24 |
Sep 18 12:44:57 PM UTC 24 |
1599376846 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.566506843 |
|
|
Sep 18 12:44:44 PM UTC 24 |
Sep 18 12:44:58 PM UTC 24 |
1167829768 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.626962276 |
|
|
Sep 18 12:44:56 PM UTC 24 |
Sep 18 12:44:59 PM UTC 24 |
33256435 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.1241124252 |
|
|
Sep 18 12:44:44 PM UTC 24 |
Sep 18 12:45:00 PM UTC 24 |
519980828 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.4155745141 |
|
|
Sep 18 12:44:44 PM UTC 24 |
Sep 18 12:45:00 PM UTC 24 |
1755164175 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.2840614953 |
|
|
Sep 18 12:44:34 PM UTC 24 |
Sep 18 12:45:01 PM UTC 24 |
1535480062 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.1362443446 |
|
|
Sep 18 12:44:50 PM UTC 24 |
Sep 18 12:45:01 PM UTC 24 |
286782381 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3735000172 |
|
|
Sep 18 12:44:23 PM UTC 24 |
Sep 18 12:45:02 PM UTC 24 |
4956236259 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.4293249225 |
|
|
Sep 18 12:45:01 PM UTC 24 |
Sep 18 12:45:03 PM UTC 24 |
22369083 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1827565953 |
|
|
Sep 18 12:45:02 PM UTC 24 |
Sep 18 12:45:05 PM UTC 24 |
22029422 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.2375554003 |
|
|
Sep 18 12:45:02 PM UTC 24 |
Sep 18 12:45:06 PM UTC 24 |
55146575 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.3327465936 |
|
|
Sep 18 12:44:56 PM UTC 24 |
Sep 18 12:45:06 PM UTC 24 |
279535481 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.2449716229 |
|
|
Sep 18 12:44:48 PM UTC 24 |
Sep 18 12:45:07 PM UTC 24 |
307667433 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.2601338898 |
|
|
Sep 18 12:44:58 PM UTC 24 |
Sep 18 12:45:08 PM UTC 24 |
467335889 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.1449787711 |
|
|
Sep 18 12:44:40 PM UTC 24 |
Sep 18 12:45:09 PM UTC 24 |
214263288 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.3012933765 |
|
|
Sep 18 12:45:05 PM UTC 24 |
Sep 18 12:45:10 PM UTC 24 |
54034139 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3736203038 |
|
|
Sep 18 12:44:50 PM UTC 24 |
Sep 18 12:45:10 PM UTC 24 |
573818413 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.910173642 |
|
|
Sep 18 12:44:58 PM UTC 24 |
Sep 18 12:45:10 PM UTC 24 |
313259661 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.630530599 |
|
|
Sep 18 12:44:59 PM UTC 24 |
Sep 18 12:45:10 PM UTC 24 |
404307919 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.1906029039 |
|
|
Sep 18 12:44:51 PM UTC 24 |
Sep 18 12:45:13 PM UTC 24 |
747409252 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.571170576 |
|
|
Sep 18 12:45:12 PM UTC 24 |
Sep 18 12:45:14 PM UTC 24 |
17950068 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.38155577 |
|
|
Sep 18 12:45:12 PM UTC 24 |
Sep 18 12:45:14 PM UTC 24 |
56532510 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.2261485943 |
|
|
Sep 18 12:44:57 PM UTC 24 |
Sep 18 12:45:18 PM UTC 24 |
517020035 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.962339257 |
|
|
Sep 18 12:45:14 PM UTC 24 |
Sep 18 12:45:18 PM UTC 24 |
23447511 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.4054676398 |
|
|
Sep 18 12:44:29 PM UTC 24 |
Sep 18 12:45:18 PM UTC 24 |
1605299646 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.1238859850 |
|
|
Sep 18 12:44:57 PM UTC 24 |
Sep 18 12:45:19 PM UTC 24 |
3602932713 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.2738096408 |
|
|
Sep 18 12:44:44 PM UTC 24 |
Sep 18 12:45:20 PM UTC 24 |
862167405 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.4153923125 |
|
|
Sep 18 12:45:08 PM UTC 24 |
Sep 18 12:45:21 PM UTC 24 |
670851356 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.3262461156 |
|
|
Sep 18 12:45:06 PM UTC 24 |
Sep 18 12:45:21 PM UTC 24 |
236592696 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.1851942663 |
|
|
Sep 18 12:45:07 PM UTC 24 |
Sep 18 12:45:22 PM UTC 24 |
314207454 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.4234836893 |
|
|
Sep 18 12:45:12 PM UTC 24 |
Sep 18 12:45:22 PM UTC 24 |
465828499 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.200194498 |
|
|
Sep 18 12:44:53 PM UTC 24 |
Sep 18 12:45:22 PM UTC 24 |
1155772597 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.3969667105 |
|
|
Sep 18 12:45:20 PM UTC 24 |
Sep 18 12:45:23 PM UTC 24 |
63975772 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.154207164 |
|
|
Sep 18 12:45:22 PM UTC 24 |
Sep 18 12:45:24 PM UTC 24 |
32964173 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.700511930 |
|
|
Sep 18 12:45:50 PM UTC 24 |
Sep 18 12:46:07 PM UTC 24 |
729575554 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.2123082740 |
|
|
Sep 18 12:45:16 PM UTC 24 |
Sep 18 12:45:25 PM UTC 24 |
249752709 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.3887165070 |
|
|
Sep 18 12:45:16 PM UTC 24 |
Sep 18 12:45:25 PM UTC 24 |
1021670556 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.541188052 |
|
|
Sep 18 12:45:31 PM UTC 24 |
Sep 18 12:46:03 PM UTC 24 |
2866847305 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3379483772 |
|
|
Sep 18 12:45:45 PM UTC 24 |
Sep 18 12:46:07 PM UTC 24 |
1059735036 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.1728397377 |
|
|
Sep 18 12:45:14 PM UTC 24 |
Sep 18 12:45:26 PM UTC 24 |
46070157 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.73478843 |
|
|
Sep 18 12:45:22 PM UTC 24 |
Sep 18 12:45:26 PM UTC 24 |
75870983 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3348019429 |
|
|
Sep 18 12:44:57 PM UTC 24 |
Sep 18 12:45:27 PM UTC 24 |
2113885909 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.871007379 |
|
|
Sep 18 12:45:10 PM UTC 24 |
Sep 18 12:45:29 PM UTC 24 |
372355923 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3849084802 |
|
|
Sep 18 12:45:24 PM UTC 24 |
Sep 18 12:45:29 PM UTC 24 |
1055556873 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.3216974742 |
|
|
Sep 18 12:43:34 PM UTC 24 |
Sep 18 12:45:29 PM UTC 24 |
17763208573 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.3209662212 |
|
|
Sep 18 12:45:14 PM UTC 24 |
Sep 18 12:45:29 PM UTC 24 |
228387880 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.3417841246 |
|
|
Sep 18 12:45:19 PM UTC 24 |
Sep 18 12:45:30 PM UTC 24 |
1022273667 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.1645123128 |
|
|
Sep 18 12:45:03 PM UTC 24 |
Sep 18 12:45:30 PM UTC 24 |
306495494 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.2743810336 |
|
|
Sep 18 12:45:09 PM UTC 24 |
Sep 18 12:45:31 PM UTC 24 |
3465617533 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.276481511 |
|
|
Sep 18 12:45:29 PM UTC 24 |
Sep 18 12:45:31 PM UTC 24 |
37483769 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1712084760 |
|
|
Sep 18 12:45:31 PM UTC 24 |
Sep 18 12:45:33 PM UTC 24 |
11139058 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.3236976912 |
|
|
Sep 18 12:45:31 PM UTC 24 |
Sep 18 12:45:34 PM UTC 24 |
27737165 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.939261563 |
|
|
Sep 18 12:45:31 PM UTC 24 |
Sep 18 12:45:35 PM UTC 24 |
95541186 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.1791681940 |
|
|
Sep 18 12:45:53 PM UTC 24 |
Sep 18 12:46:08 PM UTC 24 |
1488898603 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.3570589629 |
|
|
Sep 18 12:45:27 PM UTC 24 |
Sep 18 12:45:36 PM UTC 24 |
291564175 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.225024871 |
|
|
Sep 18 12:45:16 PM UTC 24 |
Sep 18 12:45:37 PM UTC 24 |
1493404084 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.2637925654 |
|
|
Sep 18 12:45:25 PM UTC 24 |
Sep 18 12:45:37 PM UTC 24 |
1928196754 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.922973677 |
|
|
Sep 18 12:45:24 PM UTC 24 |
Sep 18 12:45:38 PM UTC 24 |
61176691 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.1940841859 |
|
|
Sep 18 12:44:37 PM UTC 24 |
Sep 18 12:45:38 PM UTC 24 |
8152350325 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.3401429063 |
|
|
Sep 18 12:45:26 PM UTC 24 |
Sep 18 12:45:39 PM UTC 24 |
513737162 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.507355295 |
|
|
Sep 18 12:45:14 PM UTC 24 |
Sep 18 12:45:39 PM UTC 24 |
238358895 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3323762462 |
|
|
Sep 18 12:45:26 PM UTC 24 |
Sep 18 12:45:40 PM UTC 24 |
1566935385 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.2021677523 |
|
|
Sep 18 12:45:38 PM UTC 24 |
Sep 18 12:45:41 PM UTC 24 |
26893319 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2651275170 |
|
|
Sep 18 12:45:39 PM UTC 24 |
Sep 18 12:45:42 PM UTC 24 |
13905888 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.2549863151 |
|
|
Sep 18 12:45:27 PM UTC 24 |
Sep 18 12:45:42 PM UTC 24 |
4568696716 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2574400390 |
|
|
Sep 18 12:45:19 PM UTC 24 |
Sep 18 12:45:42 PM UTC 24 |
619330910 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3037121288 |
|
|
Sep 18 12:44:46 PM UTC 24 |
Sep 18 12:46:08 PM UTC 24 |
3020102768 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.2913719222 |
|
|
Sep 18 12:45:39 PM UTC 24 |
Sep 18 12:45:43 PM UTC 24 |
117687766 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.4215115486 |
|
|
Sep 18 12:45:56 PM UTC 24 |
Sep 18 12:46:08 PM UTC 24 |
1555667013 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.990628907 |
|
|
Sep 18 12:45:31 PM UTC 24 |
Sep 18 12:45:44 PM UTC 24 |
170919229 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2281276656 |
|
|
Sep 18 12:45:32 PM UTC 24 |
Sep 18 12:45:44 PM UTC 24 |
560055369 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.215763643 |
|
|
Sep 18 12:45:32 PM UTC 24 |
Sep 18 12:45:45 PM UTC 24 |
228300792 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.4228172305 |
|
|
Sep 18 12:45:39 PM UTC 24 |
Sep 18 12:45:47 PM UTC 24 |
180419489 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.3916239726 |
|
|
Sep 18 12:45:45 PM UTC 24 |
Sep 18 12:45:47 PM UTC 24 |
97531357 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.1707522822 |
|
|
Sep 18 12:45:41 PM UTC 24 |
Sep 18 12:45:48 PM UTC 24 |
89566574 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.1190147195 |
|
|
Sep 18 12:45:34 PM UTC 24 |
Sep 18 12:45:48 PM UTC 24 |
1700930447 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2775214298 |
|
|
Sep 18 12:45:46 PM UTC 24 |
Sep 18 12:45:48 PM UTC 24 |
26531567 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.1806873509 |
|
|
Sep 18 12:45:24 PM UTC 24 |
Sep 18 12:45:48 PM UTC 24 |
951240976 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.3142281146 |
|
|
Sep 18 12:45:35 PM UTC 24 |
Sep 18 12:45:51 PM UTC 24 |
1743465673 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.948432065 |
|
|
Sep 18 12:45:45 PM UTC 24 |
Sep 18 12:45:52 PM UTC 24 |
256713329 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.1815704277 |
|
|
Sep 18 12:45:48 PM UTC 24 |
Sep 18 12:45:52 PM UTC 24 |
34187338 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.3592797718 |
|
|
Sep 18 12:45:32 PM UTC 24 |
Sep 18 12:45:53 PM UTC 24 |
863374128 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3011474858 |
|
|
Sep 18 12:45:41 PM UTC 24 |
Sep 18 12:45:53 PM UTC 24 |
238251825 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.3919864953 |
|
|
Sep 18 12:45:34 PM UTC 24 |
Sep 18 12:45:53 PM UTC 24 |
386877149 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.1514982578 |
|
|
Sep 18 12:45:43 PM UTC 24 |
Sep 18 12:45:53 PM UTC 24 |
996591882 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.990861393 |
|
|
Sep 18 12:44:52 PM UTC 24 |
Sep 18 12:45:53 PM UTC 24 |
2699045411 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.932816546 |
|
|
Sep 18 12:45:23 PM UTC 24 |
Sep 18 12:45:55 PM UTC 24 |
802562717 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.3484755111 |
|
|
Sep 18 12:45:53 PM UTC 24 |
Sep 18 12:45:56 PM UTC 24 |
80234246 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.807162697 |
|
|
Sep 18 12:45:42 PM UTC 24 |
Sep 18 12:45:57 PM UTC 24 |
468136365 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1635768443 |
|
|
Sep 18 12:45:55 PM UTC 24 |
Sep 18 12:45:57 PM UTC 24 |
37245159 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.2338422160 |
|
|
Sep 18 12:45:43 PM UTC 24 |
Sep 18 12:45:59 PM UTC 24 |
251467195 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.1270402059 |
|
|
Sep 18 12:45:55 PM UTC 24 |
Sep 18 12:46:00 PM UTC 24 |
69355873 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.2856070757 |
|
|
Sep 18 12:45:48 PM UTC 24 |
Sep 18 12:46:00 PM UTC 24 |
95263982 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.54247622 |
|
|
Sep 18 12:45:57 PM UTC 24 |
Sep 18 12:46:01 PM UTC 24 |
23434216 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.3959479819 |
|
|
Sep 18 12:44:06 PM UTC 24 |
Sep 18 12:46:02 PM UTC 24 |
3259470303 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.4112655815 |
|
|
Sep 18 12:45:50 PM UTC 24 |
Sep 18 12:46:03 PM UTC 24 |
257659326 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.272829274 |
|
|
Sep 18 12:45:43 PM UTC 24 |
Sep 18 12:46:03 PM UTC 24 |
557398685 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.2620667025 |
|
|
Sep 18 12:45:50 PM UTC 24 |
Sep 18 12:46:04 PM UTC 24 |
421960144 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.3016921451 |
|
|
Sep 18 12:46:04 PM UTC 24 |
Sep 18 12:46:07 PM UTC 24 |
126642197 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.3948350742 |
|
|
Sep 18 12:45:53 PM UTC 24 |
Sep 18 12:46:09 PM UTC 24 |
376593997 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1715190519 |
|
|
Sep 18 12:46:08 PM UTC 24 |
Sep 18 12:46:10 PM UTC 24 |
11306277 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.3151377026 |
|
|
Sep 18 12:45:39 PM UTC 24 |
Sep 18 12:46:12 PM UTC 24 |
208466418 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.1074096334 |
|
|
Sep 18 12:45:59 PM UTC 24 |
Sep 18 12:46:13 PM UTC 24 |
357541399 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.841563672 |
|
|
Sep 18 12:46:10 PM UTC 24 |
Sep 18 12:46:14 PM UTC 24 |
218953036 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.111556843 |
|
|
Sep 18 12:46:00 PM UTC 24 |
Sep 18 12:46:14 PM UTC 24 |
1825896561 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.3434128472 |
|
|
Sep 18 12:46:02 PM UTC 24 |
Sep 18 12:46:15 PM UTC 24 |
413472514 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.1538636247 |
|
|
Sep 18 12:46:05 PM UTC 24 |
Sep 18 12:46:15 PM UTC 24 |
464331013 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.2284516454 |
|
|
Sep 18 12:46:02 PM UTC 24 |
Sep 18 12:46:15 PM UTC 24 |
1226183080 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.911367927 |
|
|
Sep 18 12:45:58 PM UTC 24 |
Sep 18 12:46:16 PM UTC 24 |
656242069 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.668104742 |
|
|
Sep 18 12:46:09 PM UTC 24 |
Sep 18 12:46:17 PM UTC 24 |
91151126 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.2398469657 |
|
|
Sep 18 12:45:52 PM UTC 24 |
Sep 18 12:46:17 PM UTC 24 |
1878062867 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3123801695 |
|
|
Sep 18 12:45:45 PM UTC 24 |
Sep 18 12:46:17 PM UTC 24 |
932198494 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2173473945 |
|
|
Sep 18 12:45:37 PM UTC 24 |
Sep 18 12:46:17 PM UTC 24 |
1296724353 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.1678619795 |
|
|
Sep 18 12:46:15 PM UTC 24 |
Sep 18 12:46:18 PM UTC 24 |
44876422 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.4014666865 |
|
|
Sep 18 12:46:08 PM UTC 24 |
Sep 18 12:46:18 PM UTC 24 |
181194655 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.312026404 |
|
|
Sep 18 12:46:17 PM UTC 24 |
Sep 18 12:46:19 PM UTC 24 |
237952669 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.3356631052 |
|
|
Sep 18 12:46:17 PM UTC 24 |
Sep 18 12:46:21 PM UTC 24 |
82104821 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.90596324 |
|
|
Sep 18 12:46:49 PM UTC 24 |
Sep 18 12:47:00 PM UTC 24 |
500518853 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.4082284523 |
|
|
Sep 18 12:46:36 PM UTC 24 |
Sep 18 12:47:01 PM UTC 24 |
1021145222 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.1660416123 |
|
|
Sep 18 12:46:10 PM UTC 24 |
Sep 18 12:46:22 PM UTC 24 |
1698876051 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.2065743140 |
|
|
Sep 18 12:46:10 PM UTC 24 |
Sep 18 12:46:22 PM UTC 24 |
1016394778 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.969347795 |
|
|
Sep 18 12:43:43 PM UTC 24 |
Sep 18 12:46:23 PM UTC 24 |
7955012720 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.1879839191 |
|
|
Sep 18 12:46:18 PM UTC 24 |
Sep 18 12:46:23 PM UTC 24 |
60913724 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.2302554814 |
|
|
Sep 18 12:46:11 PM UTC 24 |
Sep 18 12:46:24 PM UTC 24 |
201749489 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.2753457803 |
|
|
Sep 18 12:45:56 PM UTC 24 |
Sep 18 12:46:24 PM UTC 24 |
212607437 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3099349533 |
|
|
Sep 18 12:45:48 PM UTC 24 |
Sep 18 12:46:25 PM UTC 24 |
1444114945 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.2587546429 |
|
|
Sep 18 12:46:23 PM UTC 24 |
Sep 18 12:46:26 PM UTC 24 |
13437296 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.3743170968 |
|
|
Sep 18 12:46:23 PM UTC 24 |
Sep 18 12:46:26 PM UTC 24 |
37531529 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1496680196 |
|
|
Sep 18 12:46:25 PM UTC 24 |
Sep 18 12:46:28 PM UTC 24 |
13365514 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.3590443942 |
|
|
Sep 18 12:44:44 PM UTC 24 |
Sep 18 12:46:29 PM UTC 24 |
4866727827 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.865916063 |
|
|
Sep 18 12:46:03 PM UTC 24 |
Sep 18 12:46:30 PM UTC 24 |
10411654858 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.2278749685 |
|
|
Sep 18 12:46:18 PM UTC 24 |
Sep 18 12:46:30 PM UTC 24 |
944938959 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.559128458 |
|
|
Sep 18 12:46:19 PM UTC 24 |
Sep 18 12:46:31 PM UTC 24 |
1691194054 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.2478245841 |
|
|
Sep 18 12:46:25 PM UTC 24 |
Sep 18 12:46:31 PM UTC 24 |
147905998 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.2412670142 |
|
|
Sep 18 12:46:28 PM UTC 24 |
Sep 18 12:46:31 PM UTC 24 |
168533498 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.2786522400 |
|
|
Sep 18 12:43:58 PM UTC 24 |
Sep 18 12:47:03 PM UTC 24 |
26080066467 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.1509038132 |
|
|
Sep 18 12:46:18 PM UTC 24 |
Sep 18 12:46:31 PM UTC 24 |
135741560 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.923697875 |
|
|
Sep 18 12:46:13 PM UTC 24 |
Sep 18 12:46:32 PM UTC 24 |
988972171 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.2868209342 |
|
|
Sep 18 12:46:31 PM UTC 24 |
Sep 18 12:46:34 PM UTC 24 |
16925462 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.1025783543 |
|
|
Sep 18 12:46:31 PM UTC 24 |
Sep 18 12:46:34 PM UTC 24 |
29423608 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1260209393 |
|
|
Sep 18 12:46:33 PM UTC 24 |
Sep 18 12:46:35 PM UTC 24 |
38818567 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.437080991 |
|
|
Sep 18 12:46:20 PM UTC 24 |
Sep 18 12:46:35 PM UTC 24 |
4676039073 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1196267621 |
|
|
Sep 18 12:47:00 PM UTC 24 |
Sep 18 12:47:02 PM UTC 24 |
49155443 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.220073451 |
|
|
Sep 18 12:46:22 PM UTC 24 |
Sep 18 12:46:36 PM UTC 24 |
713310494 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.1910690250 |
|
|
Sep 18 12:46:08 PM UTC 24 |
Sep 18 12:46:37 PM UTC 24 |
257794001 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.4032877240 |
|
|
Sep 18 12:46:25 PM UTC 24 |
Sep 18 12:46:37 PM UTC 24 |
75365621 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.3635771143 |
|
|
Sep 18 12:46:29 PM UTC 24 |
Sep 18 12:46:38 PM UTC 24 |
178622043 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.1208483737 |
|
|
Sep 18 12:47:01 PM UTC 24 |
Sep 18 12:47:04 PM UTC 24 |
55126325 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.2116735947 |
|
|
Sep 18 12:46:14 PM UTC 24 |
Sep 18 12:46:38 PM UTC 24 |
659826322 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.2179048486 |
|
|
Sep 18 12:46:28 PM UTC 24 |
Sep 18 12:46:38 PM UTC 24 |
491955168 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.1747570903 |
|
|
Sep 18 12:46:35 PM UTC 24 |
Sep 18 12:46:39 PM UTC 24 |
59389840 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.211018917 |
|
|
Sep 18 12:46:19 PM UTC 24 |
Sep 18 12:46:39 PM UTC 24 |
621296044 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2513422206 |
|
|
Sep 18 12:46:39 PM UTC 24 |
Sep 18 12:46:41 PM UTC 24 |
13256804 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.1043430670 |
|
|
Sep 18 12:46:19 PM UTC 24 |
Sep 18 12:46:41 PM UTC 24 |
444920854 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.1989665578 |
|
|
Sep 18 12:46:39 PM UTC 24 |
Sep 18 12:46:41 PM UTC 24 |
15856814 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.2201695882 |
|
|
Sep 18 12:46:39 PM UTC 24 |
Sep 18 12:46:43 PM UTC 24 |
121481075 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.884032183 |
|
|
Sep 18 12:46:30 PM UTC 24 |
Sep 18 12:46:44 PM UTC 24 |
516980295 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.235061472 |
|
|
Sep 18 12:46:43 PM UTC 24 |
Sep 18 12:46:47 PM UTC 24 |
47258544 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.621323242 |
|
|
Sep 18 12:46:26 PM UTC 24 |
Sep 18 12:46:48 PM UTC 24 |
1681449436 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.1285829097 |
|
|
Sep 18 12:46:33 PM UTC 24 |
Sep 18 12:46:49 PM UTC 24 |
91927108 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.2034065086 |
|
|
Sep 18 12:46:18 PM UTC 24 |
Sep 18 12:46:50 PM UTC 24 |
682491184 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.1099975307 |
|
|
Sep 18 12:46:38 PM UTC 24 |
Sep 18 12:46:51 PM UTC 24 |
906710683 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.2415001756 |
|
|
Sep 18 12:46:26 PM UTC 24 |
Sep 18 12:46:52 PM UTC 24 |
3554029644 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.2993793673 |
|
|
Sep 18 12:46:35 PM UTC 24 |
Sep 18 12:46:52 PM UTC 24 |
436746398 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3844126285 |
|
|
Sep 18 12:44:14 PM UTC 24 |
Sep 18 12:46:52 PM UTC 24 |
15425496863 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.1759495863 |
|
|
Sep 18 12:46:36 PM UTC 24 |
Sep 18 12:46:53 PM UTC 24 |
976031099 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.574728680 |
|
|
Sep 18 12:46:36 PM UTC 24 |
Sep 18 12:46:54 PM UTC 24 |
901774414 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.4104623680 |
|
|
Sep 18 12:46:43 PM UTC 24 |
Sep 18 12:46:55 PM UTC 24 |
71534883 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.1405186599 |
|
|
Sep 18 12:46:44 PM UTC 24 |
Sep 18 12:46:55 PM UTC 24 |
290645306 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2297748889 |
|
|
Sep 18 12:46:53 PM UTC 24 |
Sep 18 12:46:55 PM UTC 24 |
26726299 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1611869826 |
|
|
Sep 18 12:46:53 PM UTC 24 |
Sep 18 12:46:56 PM UTC 24 |
25121559 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.47459954 |
|
|
Sep 18 12:46:25 PM UTC 24 |
Sep 18 12:46:56 PM UTC 24 |
315404886 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.705521344 |
|
|
Sep 18 12:46:23 PM UTC 24 |
Sep 18 12:46:58 PM UTC 24 |
2422410063 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.3677096281 |
|
|
Sep 18 12:46:45 PM UTC 24 |
Sep 18 12:46:58 PM UTC 24 |
545756710 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.1194603150 |
|
|
Sep 18 12:46:53 PM UTC 24 |
Sep 18 12:46:58 PM UTC 24 |
148803065 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.321324350 |
|
|
Sep 18 12:46:37 PM UTC 24 |
Sep 18 12:46:59 PM UTC 24 |
7458293967 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.361903019 |
|
|
Sep 18 12:46:55 PM UTC 24 |
Sep 18 12:46:59 PM UTC 24 |
50788771 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.1168658727 |
|
|
Sep 18 12:46:43 PM UTC 24 |
Sep 18 12:47:01 PM UTC 24 |
262461849 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.487433418 |
|
|
Sep 18 12:46:56 PM UTC 24 |
Sep 18 12:47:02 PM UTC 24 |
329826533 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.930814953 |
|
|
Sep 18 12:46:33 PM UTC 24 |
Sep 18 12:47:04 PM UTC 24 |
1353217114 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3020187993 |
|
|
Sep 18 12:47:02 PM UTC 24 |
Sep 18 12:47:04 PM UTC 24 |
96960131 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.1777051768 |
|
|
Sep 18 12:41:46 PM UTC 24 |
Sep 18 12:47:06 PM UTC 24 |
6049960357 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.3628442971 |
|
|
Sep 18 12:47:03 PM UTC 24 |
Sep 18 12:47:07 PM UTC 24 |
24408379 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.4087326227 |
|
|
Sep 18 12:46:56 PM UTC 24 |
Sep 18 12:47:07 PM UTC 24 |
8396592792 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.1335107087 |
|
|
Sep 18 12:46:49 PM UTC 24 |
Sep 18 12:47:08 PM UTC 24 |
500016979 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.1351269873 |
|
|
Sep 18 12:46:57 PM UTC 24 |
Sep 18 12:47:09 PM UTC 24 |
315243133 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.278240342 |
|
|
Sep 18 12:47:00 PM UTC 24 |
Sep 18 12:47:10 PM UTC 24 |
760577189 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.1637879722 |
|
|
Sep 18 12:47:05 PM UTC 24 |
Sep 18 12:47:10 PM UTC 24 |
164186037 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.820591655 |
|
|
Sep 18 12:46:40 PM UTC 24 |
Sep 18 12:47:10 PM UTC 24 |
394102076 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.2957677921 |
|
|
Sep 18 12:46:48 PM UTC 24 |
Sep 18 12:47:12 PM UTC 24 |
2166746911 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2382458972 |
|
|
Sep 18 12:47:10 PM UTC 24 |
Sep 18 12:47:12 PM UTC 24 |
207260043 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.1532537655 |
|
|
Sep 18 12:46:56 PM UTC 24 |
Sep 18 12:47:13 PM UTC 24 |
377705871 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.830233804 |
|
|
Sep 18 12:47:00 PM UTC 24 |
Sep 18 12:47:13 PM UTC 24 |
213868069 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.199154003 |
|
|
Sep 18 12:47:11 PM UTC 24 |
Sep 18 12:47:14 PM UTC 24 |
39962957 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.1084951674 |
|
|
Sep 18 12:46:57 PM UTC 24 |
Sep 18 12:47:15 PM UTC 24 |
458542923 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.4054150905 |
|
|
Sep 18 12:47:02 PM UTC 24 |
Sep 18 12:47:15 PM UTC 24 |
100399638 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.1404472317 |
|
|
Sep 18 12:47:43 PM UTC 24 |
Sep 18 12:48:01 PM UTC 24 |
789183853 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.1176011793 |
|
|
Sep 18 12:47:11 PM UTC 24 |
Sep 18 12:47:16 PM UTC 24 |
479356804 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.2793349265 |
|
|
Sep 18 12:47:13 PM UTC 24 |
Sep 18 12:47:17 PM UTC 24 |
133341376 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.931282351 |
|
|
Sep 18 12:47:06 PM UTC 24 |
Sep 18 12:47:17 PM UTC 24 |
226941221 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.1497685857 |
|
|
Sep 18 12:47:11 PM UTC 24 |
Sep 18 12:47:19 PM UTC 24 |
98819247 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.4223958617 |
|
|
Sep 18 12:47:18 PM UTC 24 |
Sep 18 12:47:21 PM UTC 24 |
25062754 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.636851265 |
|
|
Sep 18 12:47:05 PM UTC 24 |
Sep 18 12:47:21 PM UTC 24 |
354509255 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.708775236 |
|
|
Sep 18 12:47:18 PM UTC 24 |
Sep 18 12:47:21 PM UTC 24 |
78870310 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2406583410 |
|
|
Sep 18 12:47:20 PM UTC 24 |
Sep 18 12:47:22 PM UTC 24 |
77932405 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1653081714 |
|
|
Sep 18 12:46:53 PM UTC 24 |
Sep 18 12:47:22 PM UTC 24 |
329037598 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.3746747497 |
|
|
Sep 18 12:47:04 PM UTC 24 |
Sep 18 12:47:23 PM UTC 24 |
2372910176 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.2665187513 |
|
|
Sep 18 12:47:08 PM UTC 24 |
Sep 18 12:47:24 PM UTC 24 |
661934271 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3337050067 |
|
|
Sep 18 12:47:08 PM UTC 24 |
Sep 18 12:47:25 PM UTC 24 |
2570920950 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.521819574 |
|
|
Sep 18 12:47:14 PM UTC 24 |
Sep 18 12:47:25 PM UTC 24 |
351981059 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.457138660 |
|
|
Sep 18 12:47:22 PM UTC 24 |
Sep 18 12:47:26 PM UTC 24 |
316066678 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.3674983788 |
|
|
Sep 18 12:44:23 PM UTC 24 |
Sep 18 12:47:29 PM UTC 24 |
141204902699 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3377606817 |
|
|
Sep 18 12:46:23 PM UTC 24 |
Sep 18 12:47:29 PM UTC 24 |
2092636470 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2969778726 |
|
|
Sep 18 12:47:14 PM UTC 24 |
Sep 18 12:47:30 PM UTC 24 |
1255071939 ps |