Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	774088	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

964808

1

T1

7

T2

1

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1442777	1			T1	20		T2	2		T3	27
values[0x0]	147503	1			T1	4		T3	5		T4	42
values[0x1]	148616	1			T1	4		T2	1		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	611939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1126957

1

T1

12

T2

2

T3

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6100	1			T14	6		T23	5		T21	1
valid_sources[0x01]	6121	1			T12	2		T14	10		T18	7
valid_sources[0x02]	10942	1			T14	19		T23	1		T18	7
valid_sources[0x03]	5678	1			T14	16		T23	1		T18	4
valid_sources[0x04]	5360	1			T14	22		T23	1		T21	1
valid_sources[0x05]	5424	1			T14	17		T23	2		T21	4
valid_sources[0x06]	6119	1			T14	16		T21	2		T18	7
valid_sources[0x07]	5791	1			T3	1		T14	9		T23	2
valid_sources[0x08]	10853	1			T12	2		T14	12		T23	2
valid_sources[0x09]	5274	1			T14	6		T23	3		T21	1
valid_sources[0x0a]	5821	1			T14	27		T18	8		T7	2
valid_sources[0x0b]	5909	1			T14	10		T23	1		T21	2
valid_sources[0x0c]	7286	1			T14	11		T21	1		T18	5
valid_sources[0x0d]	9304	1			T14	13		T23	2		T18	8
valid_sources[0x0e]	7765	1			T14	17		T23	3		T21	4
valid_sources[0x0f]	10944	1			T3	1		T12	2		T14	14
valid_sources[0x10]	5868	1			T14	16		T23	2		T18	1
valid_sources[0x11]	8591	1			T3	1		T14	7		T21	3
valid_sources[0x12]	6081	1			T14	11		T23	2		T21	1
valid_sources[0x13]	5155	1			T14	14		T21	2		T18	8
valid_sources[0x14]	5760	1			T14	16		T23	1		T18	5
valid_sources[0x15]	7672	1			T14	27		T23	2		T18	5
valid_sources[0x16]	5738	1			T14	15		T19	6		T20	11
valid_sources[0x17]	7767	1			T14	13		T23	2		T18	5
valid_sources[0x18]	5406	1			T14	14		T18	6		T7	1
valid_sources[0x19]	5090	1			T14	18		T23	1		T18	2
valid_sources[0x1a]	5704	1			T14	5		T21	1		T18	5
valid_sources[0x1b]	6083	1			T6	1		T14	18		T34	2
valid_sources[0x1c]	5549	1			T3	1		T14	21		T21	6
valid_sources[0x1d]	6206	1			T14	18		T23	5		T18	6
valid_sources[0x1e]	5688	1			T14	9		T23	3		T18	5
valid_sources[0x1f]	7254	1			T14	8		T23	3		T21	2
valid_sources[0x20]	5898	1			T14	17		T23	5		T18	7
valid_sources[0x21]	8771	1			T14	12		T18	11		T7	1
valid_sources[0x22]	5815	1			T14	12		T23	2		T21	4
valid_sources[0x23]	5427	1			T14	19		T23	2		T21	3
valid_sources[0x24]	5687	1			T3	1		T13	52		T14	16
valid_sources[0x25]	5509	1			T14	11		T18	4		T7	2
valid_sources[0x26]	5730	1			T14	4		T18	9		T7	1
valid_sources[0x27]	5251	1			T14	13		T23	1		T21	1
valid_sources[0x28]	5735	1			T14	12		T23	1		T21	2
valid_sources[0x29]	7039	1			T14	19		T21	1		T18	7
valid_sources[0x2a]	6905	1			T14	22		T18	2		T19	7
valid_sources[0x2b]	7734	1			T14	4		T23	1		T21	2
valid_sources[0x2c]	6290	1			T14	21		T23	1		T21	1
valid_sources[0x2d]	6007	1			T14	30		T23	1		T18	10
valid_sources[0x2e]	5908	1			T14	12		T23	1		T18	3
valid_sources[0x2f]	5647	1			T14	12		T21	2		T18	7
valid_sources[0x30]	5546	1			T14	13		T23	5		T18	12
valid_sources[0x31]	12893	1			T3	2		T14	6		T23	2
valid_sources[0x32]	6017	1			T14	17		T23	1		T18	2
valid_sources[0x33]	5608	1			T14	19		T21	1		T18	5
valid_sources[0x34]	5753	1			T14	8		T21	2		T18	7
valid_sources[0x35]	5435	1			T3	2		T14	14		T18	7
valid_sources[0x36]	5901	1			T14	7		T23	1		T18	8
valid_sources[0x37]	5876	1			T14	19		T21	3		T18	3
valid_sources[0x38]	9817	1			T14	24		T23	1		T21	1
valid_sources[0x39]	6750	1			T14	9		T21	2		T18	7
valid_sources[0x3a]	6630	1			T14	5		T23	2		T21	2
valid_sources[0x3b]	6142	1			T14	9		T23	2		T21	1
valid_sources[0x3c]	5918	1			T3	1		T14	5		T23	3
valid_sources[0x3d]	7894	1			T14	31		T23	3		T21	1
valid_sources[0x3e]	5996	1			T14	22		T23	2		T18	7
valid_sources[0x3f]	5366	1			T14	18		T18	8		T7	1
valid_sources[0x40]	9075	1			T14	15		T18	7		T19	2
valid_sources[0x41]	4913	1			T14	8		T21	4		T18	8
valid_sources[0x42]	5371	1			T14	11		T18	11		T7	1
valid_sources[0x43]	5811	1			T14	21		T21	2		T18	7
valid_sources[0x44]	5811	1			T14	10		T23	1		T18	5
valid_sources[0x45]	5844	1			T14	26		T23	2		T21	1
valid_sources[0x46]	5658	1			T14	21		T21	1		T18	8
valid_sources[0x47]	5320	1			T6	2		T14	24		T23	1
valid_sources[0x48]	5743	1			T14	17		T21	1		T18	9
valid_sources[0x49]	5383	1			T3	1		T14	12		T18	4
valid_sources[0x4a]	5745	1			T14	16		T18	3		T19	3
valid_sources[0x4b]	5269	1			T14	4		T23	4		T21	1
valid_sources[0x4c]	5602	1			T14	30		T23	1		T21	2
valid_sources[0x4d]	6150	1			T14	21		T23	5		T21	1
valid_sources[0x4e]	5522	1			T14	6		T23	2		T21	1
valid_sources[0x4f]	5775	1			T6	1		T14	1		T23	2
valid_sources[0x50]	5507	1			T14	11		T23	1		T18	4
valid_sources[0x51]	5708	1			T14	9		T21	1		T18	6
valid_sources[0x52]	5428	1			T14	25		T21	1		T18	2
valid_sources[0x53]	5628	1			T14	14		T18	1		T7	1
valid_sources[0x54]	5501	1			T6	5		T14	11		T23	1
valid_sources[0x55]	7844	1			T14	6		T21	1		T18	6
valid_sources[0x56]	6579	1			T14	13		T23	3		T21	1
valid_sources[0x57]	6195	1			T14	8		T23	1		T18	3
valid_sources[0x58]	12178	1			T14	21		T23	1		T21	4
valid_sources[0x59]	5971	1			T3	1		T14	6		T23	2
valid_sources[0x5a]	7858	1			T14	9		T23	2		T18	7
valid_sources[0x5b]	7536	1			T14	32		T23	1		T21	1
valid_sources[0x5c]	5603	1			T14	17		T23	1		T21	2
valid_sources[0x5d]	5832	1			T14	5		T23	1		T21	1
valid_sources[0x5e]	5372	1			T12	1		T14	4		T21	2
valid_sources[0x5f]	5509	1			T14	6		T23	1		T21	1
valid_sources[0x60]	5587	1			T14	8		T21	1		T18	5
valid_sources[0x61]	9023	1			T14	15		T21	1		T18	2
valid_sources[0x62]	5762	1			T14	7		T23	2		T21	5
valid_sources[0x63]	6102	1			T14	15		T23	1		T21	1
valid_sources[0x64]	5562	1			T14	13		T23	2		T21	2
valid_sources[0x65]	5587	1			T3	1		T14	6		T23	1
valid_sources[0x66]	5701	1			T14	4		T23	2		T21	1
valid_sources[0x67]	5549	1			T14	4		T23	3		T21	2
valid_sources[0x68]	6195	1			T14	11		T18	4		T19	4
valid_sources[0x69]	5371	1			T14	20		T21	3		T18	5
valid_sources[0x6a]	5963	1			T14	8		T23	2		T21	1
valid_sources[0x6b]	7349	1			T14	7		T18	5		T7	1
valid_sources[0x6c]	5932	1			T14	10		T22	272		T18	4
valid_sources[0x6d]	7008	1			T14	9		T23	3		T18	5
valid_sources[0x6e]	5629	1			T14	6		T23	1		T21	2
valid_sources[0x6f]	5618	1			T14	3		T23	1		T21	1
valid_sources[0x70]	5854	1			T14	6		T23	3		T21	1
valid_sources[0x71]	5670	1			T14	15		T23	2		T21	1
valid_sources[0x72]	5548	1			T14	4		T18	2		T19	8
valid_sources[0x73]	5945	1			T6	1		T14	14		T23	1
valid_sources[0x74]	5924	1			T13	100		T14	10		T21	3
valid_sources[0x75]	23838	1			T14	30		T18	5		T19	5
valid_sources[0x76]	5778	1			T14	10		T23	2		T21	2
valid_sources[0x77]	5219	1			T14	6		T23	2		T18	8
valid_sources[0x78]	6250	1			T14	7		T23	1		T18	7
valid_sources[0x79]	7810	1			T14	13		T23	6		T18	4
valid_sources[0x7a]	7174	1			T14	9		T18	6		T7	5
valid_sources[0x7b]	6757	1			T14	11		T23	2		T18	10
valid_sources[0x7c]	6570	1			T14	7		T23	4		T21	4
valid_sources[0x7d]	6320	1			T14	10		T18	8		T7	2
valid_sources[0x7e]	5735	1			T3	1		T14	3		T23	1
valid_sources[0x7f]	6171	1			T2	1		T14	6		T21	3
valid_sources[0x80]	5424	1			T14	7		T21	1		T18	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

709970

1

T2

1

T3

17

T4

178

values[0x0]

all_enables

biggest_size

127859

1

T1

4

T3

4

T4

39

values[0x1]

all_enables

biggest_size

126979

1

T1

3

T3

2

T4

27