Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync	100.00	100.00					100.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack	100.00	100.00					100.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf	100.00	100.00					100.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid	100.00	100.00					100.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid	100.00	100.00					100.00
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack	100.00	100.00					100.00
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_lc_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.67	98.17	91.67		100.00	98.53	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.67	98.17	91.67		100.00	98.53	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.67	98.17	91.67		100.00	98.53	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.67	98.17	91.67		100.00	98.53	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.67	98.17	91.67		100.00	98.53	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.67	98.17	91.67		100.00	98.53	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prim_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=4,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        4/4              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        3/3              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T17 T52 T53 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        4/4              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53 

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=8,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T17 T52 T53 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        8/8              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53 

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack

SCORE	LINE
100.00	100.00

tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	5733	5733	0	0
OutputsKnown_A	396972738	374419976	0	0
gen_flops.OutputDelay_A	170028427	160001433	0	7266
gen_no_flops.OutputDelay_A	226944311	214031312	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5733	5733	0	0
T1	7	7	0	0
T2	7	7	0	0
T3	7	7	0	0
T4	7	7	0	0
T5	7	7	0	0
T6	7	7	0	0
T11	7	7	0	0
T12	7	7	0	0
T13	7	7	0	0
T14	7	7	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396972738	374419976	0	0
T1	9072	8666	0	0
T2	8603	8148	0	0
T3	8687	7427	0	0
T4	21042	15694	0	0
T5	147994	143934	0	0
T6	46046	45619	0	0
T11	8974	8295	0	0
T12	7847	7322	0	0
T13	16219	9695	0	0
T14	173677	170247	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170028427	160001433	0	7266
T1	3888	3705	0	9
T2	3687	3483	0	9
T3	3723	3165	0	9
T4	9018	6645	0	9
T5	63426	61614	0	9
T6	19734	19542	0	9
T11	3846	3546	0	9
T12	3363	3129	0	9
T13	6951	4047	0	9
T14	74433	72909	0	9

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226944311	214031312	0	0
T1	5184	4952	0	0
T2	4916	4656	0	0
T3	4964	4244	0	0
T4	12024	8968	0	0
T5	84568	82248	0	0
T6	26312	26068	0	0
T11	5128	4740	0	0
T12	4484	4184	0	0
T13	9268	5540	0	0
T14	99244	97284	0	0

Line Coverage for Instance : tb.dut.u_prim_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	819	819	0	0
OutputsKnown_A	57021774	53749283	0	0
gen_no_flops.OutputDelay_A	57021774	53749283	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	819	819	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57021774	53749283	0	0
T1	1296	1238	0	0
T2	1229	1164	0	0
T3	1241	1061	0	0
T4	3006	2242	0	0
T5	21142	20562	0	0
T6	6578	6517	0	0
T11	1282	1185	0	0
T12	1121	1046	0	0
T13	2317	1385	0	0
T14	24811	24321	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57021774	53749283	0	0
T1	1296	1238	0	0
T2	1229	1164	0	0
T3	1241	1061	0	0
T4	3006	2242	0	0
T5	21142	20562	0	0
T6	6578	6517	0	0
T11	1282	1185	0	0
T12	1121	1046	0	0
T13	2317	1385	0	0
T14	24811	24321	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        4/4              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	819	819	0	0
OutputsKnown_A	56741737	53525478	0	0
gen_flops.OutputDelay_A	56741737	53396295	0	2442

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	819	819	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56741737	53525478	0	0
T1	1296	1238	0	0
T2	1229	1164	0	0
T3	1241	1061	0	0
T4	3006	2242	0	0
T5	21142	20562	0	0
T6	6578	6517	0	0
T11	1282	1185	0	0
T12	1121	1046	0	0
T13	2317	1385	0	0
T14	24811	24321	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56741737	53396295	0	2442
T1	1296	1235	0	3
T2	1229	1161	0	3
T3	1241	1055	0	3
T4	3006	2215	0	3
T5	21142	20538	0	3
T6	6578	6514	0	3
T11	1282	1182	0	3
T12	1121	1043	0	3
T13	2317	1349	0	3
T14	24811	24303	0	3

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        3/3              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	819	819	0	0
OutputsKnown_A	56643345	53431593	0	0
gen_no_flops.OutputDelay_A	56643345	53431593	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	819	819	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56643345	53431593	0	0
T1	1296	1238	0	0
T2	1229	1164	0	0
T3	1241	1061	0	0
T4	3006	2242	0	0
T5	21142	20562	0	0
T6	6578	6517	0	0
T11	1282	1185	0	0
T12	1121	1046	0	0
T13	2317	1385	0	0
T14	24811	24321	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56643345	53431593	0	0
T1	1296	1238	0	0
T2	1229	1164	0	0
T3	1241	1061	0	0
T4	3006	2242	0	0
T5	21142	20562	0	0
T6	6578	6517	0	0
T11	1282	1185	0	0
T12	1121	1046	0	0
T13	2317	1385	0	0
T14	24811	24321	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T17 T52 T53 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        4/4              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53 

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	819	819	0	0
OutputsKnown_A	56633908	53420287	0	0
gen_no_flops.OutputDelay_A	56633908	53420287	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	819	819	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56633908	53420287	0	0
T1	1296	1238	0	0
T2	1229	1164	0	0
T3	1241	1061	0	0
T4	3006	2242	0	0
T5	21142	20562	0	0
T6	6578	6517	0	0
T11	1282	1185	0	0
T12	1121	1046	0	0
T13	2317	1385	0	0
T14	24811	24321	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56633908	53420287	0	0
T1	1296	1238	0	0
T2	1229	1164	0	0
T3	1241	1061	0	0
T4	3006	2242	0	0
T5	21142	20562	0	0
T6	6578	6517	0	0
T11	1282	1185	0	0
T12	1121	1046	0	0
T13	2317	1385	0	0
T14	24811	24321	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T17 T52 T53 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        8/8              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53  | T17 T52 T53 

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	819	819	0	0
OutputsKnown_A	56645284	53430149	0	0
gen_no_flops.OutputDelay_A	56645284	53430149	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	819	819	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56645284	53430149	0	0
T1	1296	1238	0	0
T2	1229	1164	0	0
T3	1241	1061	0	0
T4	3006	2242	0	0
T5	21142	20562	0	0
T6	6578	6517	0	0
T11	1282	1185	0	0
T12	1121	1046	0	0
T13	2317	1385	0	0
T14	24811	24321	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56645284	53430149	0	0
T1	1296	1238	0	0
T2	1229	1164	0	0
T3	1241	1061	0	0
T4	3006	2242	0	0
T5	21142	20562	0	0
T6	6578	6517	0	0
T11	1282	1185	0	0
T12	1121	1046	0	0
T13	2317	1385	0	0
T14	24811	24321	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	819	819	0	0
OutputsKnown_A	56643345	53431593	0	0
gen_flops.OutputDelay_A	56643345	53302569	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	819	819	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56643345	53431593	0	0
T1	1296	1238	0	0
T2	1229	1164	0	0
T3	1241	1061	0	0
T4	3006	2242	0	0
T5	21142	20562	0	0
T6	6578	6517	0	0
T11	1282	1185	0	0
T12	1121	1046	0	0
T13	2317	1385	0	0
T14	24811	24321	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56643345	53302569	0	2412
T1	1296	1235	0	3
T2	1229	1161	0	3
T3	1241	1055	0	3
T4	3006	2215	0	3
T5	21142	20538	0	3
T6	6578	6514	0	3
T11	1282	1182	0	3
T12	1121	1043	0	3
T13	2317	1349	0	3
T14	24811	24303	0	3

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	819	819	0	0
OutputsKnown_A	56643345	53431593	0	0
gen_flops.OutputDelay_A	56643345	53302569	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	819	819	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56643345	53431593	0	0
T1	1296	1238	0	0
T2	1229	1164	0	0
T3	1241	1061	0	0
T4	3006	2242	0	0
T5	21142	20562	0	0
T6	6578	6517	0	0
T11	1282	1185	0	0
T12	1121	1046	0	0
T13	2317	1385	0	0
T14	24811	24321	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56643345	53302569	0	2412
T1	1296	1235	0	3
T2	1229	1161	0	3
T3	1241	1055	0	3
T4	3006	2215	0	3
T5	21142	20538	0	3
T6	6578	6514	0	3
T11	1282	1182	0	3
T12	1121	1043	0	3
T13	2317	1349	0	3
T14	24811	24303	0	3