Unified Coverage Report :: Module :: prim_alert_sender

Module Definition

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Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tb.dut.gen_alert_tx[2].u_prim_alert_sender	100.00			100.00

Module Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_alert_tx[2].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00


Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T11,T86,T87	Yes	T11,T86,T87	INPUT
alert_req_i	Yes	Yes	T3,T22,T23	Yes	T3,T22,T23	INPUT
alert_ack_o	Yes	Yes	T3,T22,T23	Yes	T3,T22,T23	OUTPUT
alert_state_o	Yes	Yes	T3,T22,T23	Yes	T3,T22,T23	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T3,T11,T22	Yes	T3,T11,T22	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T3,T11,T22	Yes	T3,T11,T22	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00


Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T11,T86,T87	Yes	T11,T86,T87	INPUT
alert_req_i	Yes	Yes	T3,T21,T19	Yes	T3,T21,T19	INPUT
alert_ack_o	Yes	Yes	T3,T21,T19	Yes	T3,T21,T19	OUTPUT
alert_state_o	Yes	Yes	T3,T21,T19	Yes	T3,T21,T19	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T3,T11,T21	Yes	T3,T11,T21	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T3,T11,T21	Yes	T3,T11,T21	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00


Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T11,T86,T87	Yes	T11,T86,T87	INPUT
alert_req_i	Yes	Yes	T22,T23,T10	Yes	T22,T23,T10	INPUT
alert_ack_o	Yes	Yes	T22,T23,T10	Yes	T22,T23,T10	OUTPUT
alert_state_o	Yes	Yes	T22,T23,T10	Yes	T22,T23,T10	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T11,T22,T23	Yes	T11,T22,T23	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T11,T22,T23	Yes	T11,T22,T23	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[2].u_prim_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00


Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T11,T86,T87	Yes	T11,T86,T87	INPUT
alert_req_i	Yes	Yes	T85,T62,T63	Yes	T85,T62,T63	INPUT
alert_ack_o	Yes	Yes	T85,T62,T63	Yes	T85,T62,T63	OUTPUT
alert_state_o	Yes	Yes	T85,T62,T63	Yes	T85,T62,T63	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T11,T86,T85	Yes	T11,T86,T85	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T11,T86,T85	Yes	T11,T86,T85	OUTPUT

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