Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	59503146	14762	0	0
claim_transition_if_regwen_rd_A	59503146	1064	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59503146	14762	0	0
T51	126764	3	0	0
T63	20330	0	0	0
T73	79550	0	0	0
T88	0	4	0	0
T104	0	5	0	0
T105	0	2	0	0
T147	0	3	0	0
T148	0	1	0	0
T149	0	10	0	0
T150	0	4	0	0
T151	0	3	0	0
T152	0	1	0	0
T153	931	0	0	0
T154	5000	0	0	0
T155	40727	0	0	0
T156	36256	0	0	0
T157	76105	0	0	0
T158	4938	0	0	0
T159	30321	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59503146	1064	0	0
T105	294435	32	0	0
T107	0	18	0	0
T111	0	5	0	0
T114	0	8	0	0
T116	0	21	0	0
T160	0	13	0	0
T161	0	9	0	0
T162	0	247	0	0
T163	0	17	0	0
T164	0	36	0	0
T165	116088	0	0	0
T166	11063	0	0	0
T167	10730	0	0	0
T168	19031	0	0	0
T169	15896	0	0	0
T170	5565	0	0	0
T171	1282	0	0	0
T172	1857	0	0	0
T173	49723	0	0	0