Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.64	100.00	55.56	75.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	75.00			75.00
tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	75.00			75.00
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.00			75.00				gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.00			75.00				u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	INPUT
clk1_i	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	OUTPUT

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	40151793	40150155	0	0
selKnown1	57022722	57021084	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	40151793	40150155	0	0
T3	2	1	0	0
T4	9	8	0	0
T5	22067	22065	0	0
T6	7752	7750	0	0
T7	0	38990	0	0
T8	0	62320	0	0
T10	0	62210	0	0
T11	1	0	0	0
T12	2	0	0	0
T13	13	11	0	0
T14	7	5	0	0
T18	1	77	0	0
T19	0	66	0	0
T21	1	18	0	0
T22	13	11	0	0
T23	1	12	0	0
T29	0	30191	0	0
T30	0	98235	0	0
T31	0	60328	0	0
T32	0	55412	0	0
T33	0	48019	0	0
T34	2	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	57022722	57021084	0	0
T1	1296	1295	0	0
T2	1229	1228	0	0
T3	1241	1240	0	0
T4	3006	3005	0	0
T5	21143	21141	0	0
T6	6580	6578	0	0
T7	0	2	0	0
T9	0	2	0	0
T11	1282	1281	0	0
T12	1122	1120	0	0
T13	2318	2316	0	0
T14	24812	24810	0	0
T18	1	0	0	0
T21	1	0	0	0
T22	1	0	0	0
T23	1	0	0	0
T34	1	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	3	0	0
T38	0	3	0	0
T39	0	4	0	0
T40	0	4	0	0
T41	0	2	0	0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	INPUT
clk1_i	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T6,T5,T10	Yes	T6,T5,T7	INPUT
clk1_i	Yes	Yes	T6,T7,T8	Yes	T6,T7,T9	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T6,T5,T10	Yes	T6,T5,T7	OUTPUT

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T7
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T5,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	40107974	40107155	0	0
selKnown1	57021774	57020955	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	40107974	40107155	0	0
T5	22059	22058	0	0
T6	7751	7750	0	0
T7	0	38990	0	0
T8	0	62320	0	0
T10	0	62210	0	0
T12	1	0	0	0
T13	1	0	0	0
T14	1	0	0	0
T18	1	0	0	0
T21	1	0	0	0
T22	1	0	0	0
T23	1	0	0	0
T29	0	30191	0	0
T30	0	98235	0	0
T31	0	60328	0	0
T32	0	55412	0	0
T33	0	48019	0	0
T34	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	57021774	57020955	0	0
T1	1296	1295	0	0
T2	1229	1228	0	0
T3	1241	1240	0	0
T4	3006	3005	0	0
T5	21142	21141	0	0
T6	6578	6577	0	0
T11	1282	1281	0	0
T12	1121	1120	0	0
T13	2317	2316	0	0
T14	24811	24810	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	43819	43000	0	0
selKnown1	948	129	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	43819	43000	0	0
T3	2	1	0	0
T4	9	8	0	0
T5	8	7	0	0
T6	1	0	0	0
T11	1	0	0	0
T12	1	0	0	0
T13	12	11	0	0
T14	6	5	0	0
T18	0	77	0	0
T19	0	66	0	0
T21	0	18	0	0
T22	12	11	0	0
T23	0	12	0	0
T34	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	129	0	0
T5	1	0	0	0
T6	2	1	0	0
T7	0	2	0	0
T9	0	2	0	0
T12	1	0	0	0
T13	1	0	0	0
T14	1	0	0	0
T18	1	0	0	0
T21	1	0	0	0
T22	1	0	0	0
T23	1	0	0	0
T34	1	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	3	0	0
T38	0	3	0	0
T39	0	4	0	0
T40	0	4	0	0
T41	0	2	0	0