Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	832986	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1027753

1

T1

5

T2

164

T3

570

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1560255	1			T1	60		T2	312		T3	864
values[0x0]	150094	1			T1	1		T2	4		T3	78
values[0x1]	150390	1			T1	7		T2	6		T3	74

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	659009	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1201730

1

T1

26

T2

191

T3

666

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6487	1			T2	1		T3	3		T12	10
valid_sources[0x01]	6550	1			T1	1		T2	3		T3	3
valid_sources[0x02]	5479	1			T3	3		T4	5		T12	3
valid_sources[0x03]	8105	1			T3	2		T4	6		T12	4
valid_sources[0x04]	5353	1			T2	4		T3	8		T12	12
valid_sources[0x05]	7186	1			T2	1		T3	2		T12	5
valid_sources[0x06]	6839	1			T1	1		T2	2		T3	4
valid_sources[0x07]	69854	1			T3	3		T4	4		T12	3
valid_sources[0x08]	6129	1			T2	1		T3	4		T12	9
valid_sources[0x09]	7212	1			T2	5		T3	4		T12	3
valid_sources[0x0a]	7343	1			T2	1		T3	4		T4	12
valid_sources[0x0b]	6514	1			T3	3		T4	1		T12	20
valid_sources[0x0c]	6693	1			T1	1		T2	1		T3	3
valid_sources[0x0d]	5332	1			T2	1		T3	8		T12	1
valid_sources[0x0e]	5948	1			T1	1		T2	3		T3	2
valid_sources[0x0f]	5839	1			T2	2		T3	4		T4	4
valid_sources[0x10]	6282	1			T3	8		T12	15		T14	6
valid_sources[0x11]	5858	1			T2	1		T3	3		T4	1
valid_sources[0x12]	5935	1			T2	2		T3	4		T12	6
valid_sources[0x13]	6558	1			T2	4		T3	5		T4	1
valid_sources[0x14]	6095	1			T1	1		T3	3		T12	8
valid_sources[0x15]	9728	1			T2	3		T3	3		T4	6
valid_sources[0x16]	9544	1			T3	6		T4	7		T12	8
valid_sources[0x17]	6082	1			T2	2		T3	2		T4	3
valid_sources[0x18]	7742	1			T2	1		T3	7		T12	10
valid_sources[0x19]	5748	1			T3	2		T4	14		T12	10
valid_sources[0x1a]	6570	1			T2	3		T3	6		T4	19
valid_sources[0x1b]	6614	1			T1	1		T2	1		T3	7
valid_sources[0x1c]	5747	1			T1	2		T2	5		T3	2
valid_sources[0x1d]	7291	1			T1	1		T2	3		T3	6
valid_sources[0x1e]	5085	1			T2	1		T3	8		T12	8
valid_sources[0x1f]	5893	1			T2	1		T3	7		T4	19
valid_sources[0x20]	5719	1			T2	1		T3	3		T12	7
valid_sources[0x21]	11877	1			T2	4		T3	7		T12	7
valid_sources[0x22]	5520	1			T2	4		T3	4		T4	7
valid_sources[0x23]	10236	1			T2	1		T3	4		T12	1
valid_sources[0x24]	5675	1			T3	3		T12	12		T15	3
valid_sources[0x25]	10250	1			T2	1		T3	2		T4	3
valid_sources[0x26]	6684	1			T2	1		T3	3		T12	15
valid_sources[0x27]	10041	1			T3	3		T12	7		T14	2
valid_sources[0x28]	5990	1			T2	2		T3	10		T4	11
valid_sources[0x29]	5221	1			T3	2		T12	3		T14	10
valid_sources[0x2a]	5616	1			T2	2		T3	3		T12	17
valid_sources[0x2b]	6301	1			T1	1		T2	1		T3	4
valid_sources[0x2c]	5274	1			T3	5		T12	2		T14	1
valid_sources[0x2d]	5230	1			T2	4		T3	4		T12	5
valid_sources[0x2e]	5770	1			T2	2		T3	5		T12	7
valid_sources[0x2f]	6448	1			T1	1		T2	2		T3	3
valid_sources[0x30]	5834	1			T2	1		T3	4		T4	6
valid_sources[0x31]	5640	1			T2	1		T12	9		T14	6
valid_sources[0x32]	7314	1			T2	5		T3	7		T4	3
valid_sources[0x33]	6295	1			T2	2		T3	3		T12	13
valid_sources[0x34]	8333	1			T1	1		T2	1		T3	2
valid_sources[0x35]	5942	1			T2	2		T3	10		T12	15
valid_sources[0x36]	5393	1			T2	2		T3	3		T4	2
valid_sources[0x37]	5890	1			T3	3		T12	1		T14	2
valid_sources[0x38]	5995	1			T3	6		T4	15		T12	2
valid_sources[0x39]	6010	1			T3	3		T12	5		T14	2
valid_sources[0x3a]	7235	1			T2	1		T3	11		T4	8
valid_sources[0x3b]	5682	1			T1	1		T2	1		T3	2
valid_sources[0x3c]	8648	1			T2	1		T3	4		T12	19
valid_sources[0x3d]	6130	1			T2	1		T3	7		T12	1
valid_sources[0x3e]	7267	1			T1	1		T3	2		T12	9
valid_sources[0x3f]	5765	1			T2	1		T3	4		T12	12
valid_sources[0x40]	30867	1			T3	6		T12	7		T14	5
valid_sources[0x41]	5632	1			T1	1		T3	3		T12	4
valid_sources[0x42]	7426	1			T1	1		T2	1		T3	3
valid_sources[0x43]	7773	1			T3	5		T12	19		T14	5
valid_sources[0x44]	5671	1			T2	2		T3	5		T4	4
valid_sources[0x45]	7085	1			T2	2		T3	5		T4	7
valid_sources[0x46]	5359	1			T2	1		T3	2		T4	4
valid_sources[0x47]	5677	1			T2	1		T3	6		T12	4
valid_sources[0x48]	6581	1			T3	4		T4	13		T12	2
valid_sources[0x49]	5625	1			T3	1		T4	7		T12	1
valid_sources[0x4a]	5678	1			T2	1		T3	8		T12	10
valid_sources[0x4b]	5813	1			T2	2		T3	5		T12	10
valid_sources[0x4c]	6250	1			T2	2		T3	4		T12	16
valid_sources[0x4d]	10134	1			T2	1		T3	5		T4	3
valid_sources[0x4e]	5731	1			T3	5		T4	12		T12	6
valid_sources[0x4f]	5912	1			T2	1		T3	3		T12	4
valid_sources[0x50]	11447	1			T2	1		T3	2		T4	1
valid_sources[0x51]	6134	1			T1	1		T2	4		T3	4
valid_sources[0x52]	6218	1			T3	1		T12	5		T14	6
valid_sources[0x53]	7338	1			T3	5		T4	5		T12	4
valid_sources[0x54]	5826	1			T2	2		T3	6		T4	8
valid_sources[0x55]	6256	1			T3	3		T12	5		T14	5
valid_sources[0x56]	5498	1			T3	8		T12	11		T14	3
valid_sources[0x57]	8744	1			T1	3		T3	5		T4	1
valid_sources[0x58]	15746	1			T2	2		T3	5		T12	7
valid_sources[0x59]	7227	1			T3	7		T12	10		T14	4
valid_sources[0x5a]	7413	1			T1	1		T2	2		T3	5
valid_sources[0x5b]	5704	1			T2	2		T3	3		T12	5
valid_sources[0x5c]	6288	1			T2	1		T3	5		T4	8
valid_sources[0x5d]	5849	1			T2	2		T12	3		T14	4
valid_sources[0x5e]	5934	1			T1	1		T2	5		T4	3
valid_sources[0x5f]	5663	1			T1	1		T2	1		T3	3
valid_sources[0x60]	7237	1			T1	1		T2	1		T3	2
valid_sources[0x61]	5445	1			T2	1		T3	2		T12	12
valid_sources[0x62]	5999	1			T2	1		T3	5		T12	11
valid_sources[0x63]	5833	1			T1	1		T2	1		T3	2
valid_sources[0x64]	5873	1			T3	2		T12	11		T15	2
valid_sources[0x65]	7917	1			T2	1		T3	4		T12	11
valid_sources[0x66]	5728	1			T2	1		T3	9		T4	4
valid_sources[0x67]	5664	1			T1	1		T2	1		T3	3
valid_sources[0x68]	5730	1			T2	1		T3	7		T12	21
valid_sources[0x69]	16155	1			T1	2		T2	3		T3	1
valid_sources[0x6a]	5850	1			T3	4		T4	10		T12	3
valid_sources[0x6b]	5882	1			T1	1		T3	6		T12	12
valid_sources[0x6c]	5495	1			T3	2		T4	13		T12	6
valid_sources[0x6d]	6814	1			T1	1		T2	1		T3	6
valid_sources[0x6e]	5578	1			T1	1		T3	4		T14	2
valid_sources[0x6f]	8343	1			T12	5		T14	1		T15	9
valid_sources[0x70]	5563	1			T1	1		T2	1		T3	6
valid_sources[0x71]	5343	1			T3	3		T12	14		T14	2
valid_sources[0x72]	5670	1			T1	1		T3	9		T4	1
valid_sources[0x73]	5611	1			T1	1		T3	2		T12	7
valid_sources[0x74]	6780	1			T2	1		T3	7		T12	8
valid_sources[0x75]	6548	1			T3	4		T12	18		T14	3
valid_sources[0x76]	5815	1			T2	2		T3	2		T4	5
valid_sources[0x77]	6077	1			T3	3		T4	3		T12	10
valid_sources[0x78]	18821	1			T2	1		T3	4		T12	4
valid_sources[0x79]	5660	1			T2	3		T3	5		T4	2
valid_sources[0x7a]	9507	1			T1	1		T2	1		T3	3
valid_sources[0x7b]	6679	1			T2	1		T3	7		T12	6
valid_sources[0x7c]	5696	1			T2	1		T3	2		T12	6
valid_sources[0x7d]	6965	1			T2	1		T3	7		T12	8
valid_sources[0x7e]	5424	1			T1	1		T2	5		T3	3
valid_sources[0x7f]	5924	1			T1	1		T2	4		T3	6
valid_sources[0x80]	6370	1			T2	5		T3	5		T12	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

769163

1

T2

156

T3

433

T4

192

values[0x0]

all_enables

biggest_size

130111

1

T1

1

T2

3

T3

71

values[0x1]

all_enables

biggest_size

128479

1

T1

4

T2

5

T3

66