| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 60.00 | 60.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex | 60.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 60.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 10 | 4 | 6 | 60.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 10 | 4 | 6 | 60.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 10 | 4 | 6 | 60.00 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| others[3] | 0 | 1 | 1 | |
| others[4] | 0 | 1 | 1 | |
| others[7] | 0 | 1 | 1 | |
| false | 0 | 1 | 1 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 2742 | 1 | T7 | 40 | T8 | 260 | T9 | 18 | ||||
| others[1] | 3 | 1 | T13 | 1 | T235 | 1 | T236 | 1 | ||||
| others[2] | 2 | 1 | T237 | 1 | T238 | 1 | - | - | ||||
| others[5] | 1 | 1 | T239 | 1 | - | - | - | - | ||||
| others[6] | 1 | 1 | T161 | 1 | - | - | - | - | ||||
| true | 41600 | 1 | T1 | 1 | T2 | 2 | T3 | 19 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |