Module Definition
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Module Instance : tb.dut.u_reg.u_claim_transition_if_regwen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.77 100.00 99.07 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00



Module Instance : tb.dut.u_reg_tap.u_claim_transition_if_regwen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.73 100.00 98.92 100.00 100.00 u_reg_tap


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00

Line Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T126 T127 T122  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Module : prim_subreg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT126,T127,T122

Branch Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T126,T127,T122
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T126,T127,T122
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_claim_transition_if_regwen
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T122 T146 T123  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T122 T146 T123  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_claim_transition_if_regwen
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT122,T146,T123

Branch Coverage for Instance : tb.dut.u_reg.u_claim_transition_if_regwen
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T122,T146,T123
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T122,T146,T123
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_tap.u_claim_transition_if_regwen
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T126 T127 T118  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_tap.u_claim_transition_if_regwen
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT126,T127,T118

Branch Coverage for Instance : tb.dut.u_reg_tap.u_claim_transition_if_regwen
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T126,T127,T118
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T126,T127,T118
0 0 Covered T1,T2,T3

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