Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	59091560	14403	0	0
claim_transition_if_regwen_rd_A	59091560	1003	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59091560	14403	0	0
T93	205072	2	0	0
T94	0	2	0	0
T95	0	3	0	0
T113	0	1	0	0
T147	0	7	0	0
T148	0	6	0	0
T149	0	6	0	0
T150	0	4	0	0
T151	0	8	0	0
T152	0	1	0	0
T153	62838	0	0	0
T154	22440	0	0	0
T155	38786	0	0	0
T156	1864	0	0	0
T157	160851	0	0	0
T158	27983	0	0	0
T159	4645	0	0	0
T160	5788	0	0	0
T161	661	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59091560	1003	0	0
T78	4856	0	0	0
T122	0	25	0	0
T123	0	4	0	0
T152	250188	3	0	0
T162	0	1	0	0
T163	0	7	0	0
T164	0	1	0	0
T165	0	9	0	0
T166	0	221	0	0
T167	0	5	0	0
T168	0	2	0	0
T169	38270	0	0	0
T170	34247	0	0	0
T171	2419	0	0	0
T172	7191	0	0	0
T173	23862	0	0	0
T174	67769	0	0	0
T175	1646	0	0	0
T176	31671	0	0	0