Line Coverage for Module :
tlul_adapter_host
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 21 | 91.30 |
| ALWAYS | 70 | 3 | 3 | 100.00 |
| ALWAYS | 78 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 132 | 4 | 3 | 75.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
| ALWAYS | 168 | 0 | 0 | |
| ALWAYS | 178 | 0 | 0 | |
69 always_ff @(posedge clk_i or negedge rst_ni) begin
70 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
71 1/1 source_q <= '0;
Tests: T1 T2 T3
72 end else begin
73 1/1 source_q <= source_d;
Tests: T1 T2 T3
74 end
75 end
76
77 always_comb begin
78 1/1 source_d = source_q;
Tests: T1 T2 T3
79
80 1/1 if (req_i && gnt_o) begin
Tests: T1 T2 T3
81 1/1 if (source_q == MaxSource[ReqNumW-1:0]) begin
Tests: T1 T2 T3
82 1/1 source_d = '0;
Tests: T5 T6 T7
83 end else begin
84 1/1 source_d = source_q + ReqNumOne;
Tests: T1 T2 T3
85 end
86 end
MISSING_ELSE
87 end
88
89 1/1 assign tl_source = top_pkg::TL_AIW'(source_q);
Tests: T1 T2 T3
90 end
91
92 // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
93 // bits set. For writes the supplied be_i is used as the mask.
94 1/1 assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
Tests: T5 T6 T7
95
96 1/1 assign tl_out = '{
Tests: T1 T2 T3
97 a_valid: req_i,
98 a_opcode: (~we_i) ? Get :
99 (&be_i) ? PutFullData :
100 PutPartialData,
101 a_param: 3'h0,
102 a_size: top_pkg::TL_SZW'(WordSize),
103 a_mask: tl_be,
104 a_source: tl_source,
105 a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
106 a_data: wdata_i,
107 a_user: '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i},
108 d_ready: 1'b1
109 };
110
111 tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
112 .tl_i(tl_out),
113 .tl_o(tl_o)
114 );
115
116 1/1 assign gnt_o = tl_i.a_ready;
Tests: T1 T2 T3
117
118 1/1 assign valid_o = tl_i.d_valid;
Tests: T1 T2 T3
119 1/1 assign rdata_o = tl_i.d_data;
Tests: T1 T2 T3
120 1/1 assign rdata_intg_o = tl_i.d_user.data_intg;
Tests: T1 T2 T3
121
122 logic intg_err;
123 tlul_rsp_intg_chk #(
124 .EnableRspDataIntgCheck(EnableRspDataIntgCheck)
125 ) u_rsp_chk (
126 .tl_i,
127 .err_o(intg_err)
128 );
129
130 logic intg_err_q;
131 always_ff @(posedge clk_i or negedge rst_ni) begin
132 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
133 1/1 intg_err_q <= '0;
Tests: T1 T2 T3
134 1/1 end else if (intg_err) begin
Tests: T1 T2 T3
135 0/1 ==> intg_err_q <= 1'b1;
136 end
MISSING_ELSE
137 end
138
139 // err_o is transactional. This allows the host to continue
140 // debug without receiving an endless stream of errors.
141 1/1 assign err_o = tl_i.d_error | intg_err;
Tests: T1 T2 T3
142
143 // intg_err_o is permanent once detected, and should be used
144 // to trigger alerts
145 1/1 assign intg_err_o = intg_err_q | intg_err;
Tests: T1 T2 T3
146
147 // Addresses are assumed to be word-aligned, and the bottom bits are ignored
148 logic unused_addr_bottom_bits;
149 0/1 ==> assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
150
151 // Explicitly ignore unused fields of tl_i
152 logic unused_tl_i_fields;
153 1/1 assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
Tests: T1 T2 T3
154 tl_i.d_size, tl_i.d_source, tl_i.d_sink,
155 tl_i.d_user};
156
157 `ifdef INC_ASSERT
158 //VCS coverage off
159 // pragma coverage off
160 localparam int OutstandingReqCntW =
161 (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
162 localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1);
163
164 logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
165 logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
166
167 always_comb begin
168 unreachable outstanding_reqs_d = outstanding_reqs_q;
169
170 unreachable if ((req_i && gnt_o) && !valid_o) begin
171 unreachable outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne;
172 unreachable end else if (!(req_i && gnt_o) && valid_o) begin
173 unreachable outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne;
174 end
==> MISSING_ELSE
175 end
176
177 always_ff @(posedge clk_i or negedge rst_ni) begin
178 unreachable if (!rst_ni) begin
179 unreachable outstanding_reqs_q <= '0;
180 end else begin
181 unreachable outstanding_reqs_q <= outstanding_reqs_d;
Cond Coverage for Module :
tlul_adapter_host
| Total | Covered | Percent |
|---|
| Conditions | 16 | 11 | 68.75 |
| Logical | 16 | 11 | 68.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 80
EXPRESSION (req_i && gnt_o)
--1-- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T5,T6,T7 |
LINE 81
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
LINE 94
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T6,T7 |
| 1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T6,T7 |
| 1 | Covered | T5,T6,T7 |
LINE 96
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T5,T6,T7 |
LINE 141
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 145
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
Branch Coverage for Module :
tlul_adapter_host
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
9 |
90.00 |
| TERNARY |
94 |
2 |
2 |
100.00 |
| IF |
132 |
3 |
2 |
66.67 |
| IF |
70 |
2 |
2 |
100.00 |
| IF |
80 |
3 |
3 |
100.00 |
94 assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T6,T7 |
| 0 |
Covered |
T5,T6,T7 |
132 if (!rst_ni) begin
-1-
133 intg_err_q <= '0;
==>
134 end else if (intg_err) begin
-2-
135 intg_err_q <= 1'b1;
==>
136 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Covered |
T1,T2,T3 |
70 if (!rst_ni) begin
-1-
71 source_q <= '0;
==>
72 end else begin
73 source_q <= source_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
80 if (req_i && gnt_o) begin
-1-
81 if (source_q == MaxSource[ReqNumW-1:0]) begin
-2-
82 source_d = '0;
==>
83 end else begin
84 source_d = source_q + ReqNumOne;
==>
85 end
86 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T5,T6,T7 |
| 1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_host
Assertion Details
DontExceeedMaxReqs
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
56785484 |
211263 |
0 |
0 |
| T5 |
20480 |
161 |
0 |
0 |
| T6 |
14817 |
127 |
0 |
0 |
| T7 |
88547 |
418 |
0 |
0 |
| T8 |
74422 |
536 |
0 |
0 |
| T11 |
66092 |
336 |
0 |
0 |
| T16 |
34458 |
0 |
0 |
0 |
| T19 |
35438 |
0 |
0 |
0 |
| T20 |
4850 |
0 |
0 |
0 |
| T23 |
39281 |
0 |
0 |
0 |
| T24 |
0 |
862 |
0 |
0 |
| T25 |
0 |
371 |
0 |
0 |
| T26 |
0 |
232 |
0 |
0 |
| T27 |
0 |
325 |
0 |
0 |
| T28 |
0 |
237 |
0 |
0 |
| T29 |
1726 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tap_tlul_host
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 21 | 95.45 |
| ALWAYS | 70 | 3 | 3 | 100.00 |
| ALWAYS | 78 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 132 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
| ALWAYS | 168 | 0 | 0 | |
| ALWAYS | 178 | 0 | 0 | |
69 always_ff @(posedge clk_i or negedge rst_ni) begin
70 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
71 1/1 source_q <= '0;
Tests: T1 T2 T3
72 end else begin
73 1/1 source_q <= source_d;
Tests: T1 T2 T3
74 end
75 end
76
77 always_comb begin
78 1/1 source_d = source_q;
Tests: T1 T2 T3
79
80 1/1 if (req_i && gnt_o) begin
Tests: T1 T2 T3
81 1/1 if (source_q == MaxSource[ReqNumW-1:0]) begin
Tests: T1 T2 T3
82 1/1 source_d = '0;
Tests: T5 T6 T7
83 end else begin
84 1/1 source_d = source_q + ReqNumOne;
Tests: T1 T2 T3
85 end
86 end
MISSING_ELSE
87 end
88
89 1/1 assign tl_source = top_pkg::TL_AIW'(source_q);
Tests: T1 T2 T3
90 end
91
92 // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
93 // bits set. For writes the supplied be_i is used as the mask.
94 1/1 assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
Tests: T5 T6 T7
95
96 1/1 assign tl_out = '{
Tests: T1 T2 T3
97 a_valid: req_i,
98 a_opcode: (~we_i) ? Get :
99 (&be_i) ? PutFullData :
100 PutPartialData,
101 a_param: 3'h0,
102 a_size: top_pkg::TL_SZW'(WordSize),
103 a_mask: tl_be,
104 a_source: tl_source,
105 a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
106 a_data: wdata_i,
107 a_user: '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i},
108 d_ready: 1'b1
109 };
110
111 tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
112 .tl_i(tl_out),
113 .tl_o(tl_o)
114 );
115
116 1/1 assign gnt_o = tl_i.a_ready;
Tests: T1 T2 T3
117
118 1/1 assign valid_o = tl_i.d_valid;
Tests: T1 T2 T3
119 1/1 assign rdata_o = tl_i.d_data;
Tests: T1 T2 T3
120 1/1 assign rdata_intg_o = tl_i.d_user.data_intg;
Tests: T1 T2 T3
121
122 logic intg_err;
123 tlul_rsp_intg_chk #(
124 .EnableRspDataIntgCheck(EnableRspDataIntgCheck)
125 ) u_rsp_chk (
126 .tl_i,
127 .err_o(intg_err)
128 );
129
130 logic intg_err_q;
131 always_ff @(posedge clk_i or negedge rst_ni) begin
132 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
133 1/1 intg_err_q <= '0;
Tests: T1 T2 T3
134 1/1 end else if (intg_err) begin
Tests: T1 T2 T3
135 excluded intg_err_q <= 1'b1;
Exclude Annotation: VC_COV_UNR
136 end
MISSING_ELSE
137 end
138
139 // err_o is transactional. This allows the host to continue
140 // debug without receiving an endless stream of errors.
141 1/1 assign err_o = tl_i.d_error | intg_err;
Tests: T1 T2 T3
142
143 // intg_err_o is permanent once detected, and should be used
144 // to trigger alerts
145 1/1 assign intg_err_o = intg_err_q | intg_err;
Tests: T1 T2 T3
146
147 // Addresses are assumed to be word-aligned, and the bottom bits are ignored
148 logic unused_addr_bottom_bits;
149 0/1 ==> assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
150
151 // Explicitly ignore unused fields of tl_i
152 logic unused_tl_i_fields;
153 1/1 assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
Tests: T1 T2 T3
154 tl_i.d_size, tl_i.d_source, tl_i.d_sink,
155 tl_i.d_user};
156
157 `ifdef INC_ASSERT
158 //VCS coverage off
159 // pragma coverage off
160 localparam int OutstandingReqCntW =
161 (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
162 localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1);
163
164 logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
165 logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
166
167 always_comb begin
168 unreachable outstanding_reqs_d = outstanding_reqs_q;
169
170 unreachable if ((req_i && gnt_o) && !valid_o) begin
171 unreachable outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne;
172 unreachable end else if (!(req_i && gnt_o) && valid_o) begin
173 unreachable outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne;
174 end
==> MISSING_ELSE
175 end
176
177 always_ff @(posedge clk_i or negedge rst_ni) begin
178 unreachable if (!rst_ni) begin
179 unreachable outstanding_reqs_q <= '0;
180 end else begin
181 unreachable outstanding_reqs_q <= outstanding_reqs_d;
Cond Coverage for Instance : tb.dut.u_tap_tlul_host
| Total | Covered | Percent |
|---|
| Conditions | 12 | 11 | 91.67 |
| Logical | 12 | 11 | 91.67 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 80
EXPRESSION (req_i && gnt_o)
--1-- --2--
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T5,T6,T7 |
LINE 81
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
LINE 94
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T6,T7 |
| 1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T6,T7 |
| 1 | Covered | T5,T6,T7 |
LINE 96
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T5,T6,T7 |
LINE 141
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Not Covered | |
LINE 145
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Excluded | |
VC_COV_UNR |
Branch Coverage for Instance : tb.dut.u_tap_tlul_host
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
94 |
2 |
2 |
100.00 |
| IF |
132 |
2 |
2 |
100.00 |
| IF |
70 |
2 |
2 |
100.00 |
| IF |
80 |
3 |
3 |
100.00 |
94 assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T6,T7 |
| 0 |
Covered |
T5,T6,T7 |
132 if (!rst_ni) begin
-1-
133 intg_err_q <= '0;
==>
134 end else if (intg_err) begin
-2-
135 intg_err_q <= 1'b1;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
136 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Covered |
T1,T2,T3 |
|
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
70 if (!rst_ni) begin
-1-
71 source_q <= '0;
==>
72 end else begin
73 source_q <= source_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
80 if (req_i && gnt_o) begin
-1-
81 if (source_q == MaxSource[ReqNumW-1:0]) begin
-2-
82 source_d = '0;
==>
83 end else begin
84 source_d = source_q + ReqNumOne;
==>
85 end
86 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T5,T6,T7 |
| 1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tap_tlul_host
Assertion Details
DontExceeedMaxReqs
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
56785484 |
211263 |
0 |
0 |
| T5 |
20480 |
161 |
0 |
0 |
| T6 |
14817 |
127 |
0 |
0 |
| T7 |
88547 |
418 |
0 |
0 |
| T8 |
74422 |
536 |
0 |
0 |
| T11 |
66092 |
336 |
0 |
0 |
| T16 |
34458 |
0 |
0 |
0 |
| T19 |
35438 |
0 |
0 |
0 |
| T20 |
4850 |
0 |
0 |
0 |
| T23 |
39281 |
0 |
0 |
0 |
| T24 |
0 |
862 |
0 |
0 |
| T25 |
0 |
371 |
0 |
0 |
| T26 |
0 |
232 |
0 |
0 |
| T27 |
0 |
325 |
0 |
0 |
| T28 |
0 |
237 |
0 |
0 |
| T29 |
1726 |
0 |
0 |
0 |