Unified Coverage Report :: Module :: tlul_err

Module : tlul_err

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_tap.u_reg_if.u_err	97.50	90.00	100.00			100.00	100.00
tb.dut.u_reg.u_reg_if.u_err	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg_tap.u_reg_if.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	90.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	90.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.91	97.37	94.29			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_reg_if.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.44	100.00	97.78			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	57	17	17	100.00
CONT_ASSIGN	96	1	1	100.00

25                        logic op_full, op_partial, op_get;
26         1/1            assign op_full    = (tl_i.a_opcode == PutFullData);
           Tests:       T1 T2 T3 
27         1/1            assign op_partial = (tl_i.a_opcode == PutPartialData);
           Tests:       T1 T2 T3 
28         1/1            assign op_get     = (tl_i.a_opcode == Get);
           Tests:       T1 T2 T3 
29                      
30                        // An instruction type transaction cannot be write
31                        logic instr_wr_err;
32         1/1            assign instr_wr_err = prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) &
           Tests:       T1 T2 T3 
33                                              (op_full | op_partial);
34                      
35                        logic instr_type_err;
36         1/1            assign instr_type_err = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type);
           Tests:       T1 T2 T3 
37                      
38                        // Anything that doesn't fall into the permitted category, it raises an error
39         1/1            assign err_o = ~(opcode_allowed & a_config_allowed) | instr_wr_err | instr_type_err;
           Tests:       T1 T2 T3 
40                      
41                        // opcode check
42         1/1            assign opcode_allowed = (tl_i.a_opcode == PutFullData)
           Tests:       T1 T2 T3 
43                                              | (tl_i.a_opcode == PutPartialData)
44                                              | (tl_i.a_opcode == Get);
45                      
46                        // a channel configuration check
47                        logic addr_sz_chk;    // address and size alignment check
48                        logic mask_chk;       // inactive lane a_mask check
49                        logic fulldata_chk;   // PutFullData should have size match to mask
50                      
51                        localparam bit [MW-1:0] MaskOne = 1;
52                        logic [MW-1:0] mask;
53                      
54         1/1            assign mask = MaskOne << tl_i.a_address[SubAW-1:0];
           Tests:       T1 T2 T3 
55                      
56                        always_comb begin
57         1/1              addr_sz_chk  = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              mask_chk     = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              fulldata_chk = 1'b0; // Only valid when opcode is PutFullData
           Tests:       T1 T2 T3 
60                      
61         1/1              if (tl_i.a_valid) begin
           Tests:       T1 T2 T3 
62         1/1                unique case (tl_i.a_size)
           Tests:       T1 T2 T3 
63                              'h0: begin // 1 Byte
64         1/1                    addr_sz_chk  = 1'b1;
           Tests:       T1 T2 T3 
65         1/1                    mask_chk     = ~|(tl_i.a_mask & ~mask);
           Tests:       T1 T2 T3 
66         1/1                    fulldata_chk = |(tl_i.a_mask & mask);
           Tests:       T1 T2 T3 
67                              end
68                      
69                              'h1: begin // 2 Byte
70         1/1                    addr_sz_chk  = ~tl_i.a_address[0];
           Tests:       T1 T2 T3 
71                                // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
72         1/1                    mask_chk     = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
           Tests:       T1 T2 T3 
73                                             : ~|(tl_i.a_mask & 4'b1100);
74         1/1                    fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
           Tests:       T1 T2 T3 
75                              end
76                      
77                              'h2: begin // 4 Byte
78         1/1                    addr_sz_chk  = ~|tl_i.a_address[SubAW-1:0];
           Tests:       T1 T2 T3 
79         1/1                    mask_chk     = 1'b1;
           Tests:       T1 T2 T3 
80         1/1                    fulldata_chk = &tl_i.a_mask[3:0];
           Tests:       T1 T2 T3 
81                              end
82                      
83                              default: begin // else
84                                addr_sz_chk  = 1'b0;
85                                mask_chk     = 1'b0;
86                                fulldata_chk = 1'b0;
87                              end
88                            endcase
89                          end else begin
90         1/1                addr_sz_chk  = 1'b0;
           Tests:       T1 T2 T3 
91         1/1                mask_chk     = 1'b0;
           Tests:       T1 T2 T3 
92         1/1                fulldata_chk = 1'b0;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96         1/1            assign a_config_allowed = addr_sz_chk
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : tlul_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T93,T94,T95
0	1	0	Covered	T93,T94,T95
1	0	0	Covered	T1,T2,T3

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T114,T121,T125
1	0	Covered	T5,T16,T6
1	1	Covered	T1,T2,T3

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T148,T117,T99
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T95,T117,T163
1	0	1	Covered	T148,T152,T198
1	1	0	Covered	T117,T99,T208
1	1	1	Covered	T1,T2,T3

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T16,T6
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	61	8	8	100.00

61             if (tl_i.a_valid) begin
               -1-  
62               unique case (tl_i.a_size)
                        -2-  
63                 'h0: begin // 1 Byte
64                   addr_sz_chk  = 1'b1;
                     ==>
65                   mask_chk     = ~|(tl_i.a_mask & ~mask);
66                   fulldata_chk = |(tl_i.a_mask & mask);
67                 end
68         
69                 'h1: begin // 2 Byte
70                   addr_sz_chk  = ~tl_i.a_address[0];
71                   // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
72                   mask_chk     = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
                                                        -3-  
                                                        ==>  
                                                        ==>  
73                                : ~|(tl_i.a_mask & 4'b1100);
74                   fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
                                                        -4-  
                                                        ==>  
                                                        ==>  
75                 end
76         
77                 'h2: begin // 4 Byte
78                   addr_sz_chk  = ~|tl_i.a_address[SubAW-1:0];
                     ==>
79                   mask_chk     = 1'b1;
80                   fulldata_chk = &tl_i.a_mask[3:0];
81                 end
82         
83                 default: begin // else
84                   addr_sz_chk  = 1'b0;
                     ==>
85                   mask_chk     = 1'b0;
86                   fulldata_chk = 1'b0;
87                 end
88               endcase
89             end else begin
90               addr_sz_chk  = 1'b0;
                 ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T1,T2,T3
1	'h1	1	-	Covered	T2,T3,T4
1	'h1	0	-	Covered	T1,T2,T3
1	'h1	-	1	Covered	T2,T3,T4
1	'h1	-	0	Covered	T1,T2,T3
1	'h00000002	-	-	Covered	T1,T2,T3
1	default	-	-	Covered	T148,T198,T162
0	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	2022	2022	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2022	2022	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T12	2	2	0	0
T13	2	2	0	0
T14	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0

Line Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err

	Line No.	Total	Covered	Percent
TOTAL		20	18	90.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	0	0.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	54	1	0	0.00
ALWAYS	57	11	11	100.00
CONT_ASSIGN	96	1	1	100.00

25                        logic op_full, op_partial, op_get;
26         1/1            assign op_full    = (tl_i.a_opcode == PutFullData);
           Tests:       T5 T6 T7 
27         1/1            assign op_partial = (tl_i.a_opcode == PutPartialData);
           Tests:       T5 T6 T7 
28         1/1            assign op_get     = (tl_i.a_opcode == Get);
           Tests:       T5 T6 T7 
29                      
30                        // An instruction type transaction cannot be write
31                        logic instr_wr_err;
32         1/1            assign instr_wr_err = prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) &
           Tests:       T5 T6 T7 
33                                              (op_full | op_partial);
34                      
35                        logic instr_type_err;
36         0/1     ==>    assign instr_type_err = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type);
37                      
38                        // Anything that doesn't fall into the permitted category, it raises an error
39         1/1            assign err_o = ~(opcode_allowed & a_config_allowed) | instr_wr_err | instr_type_err;
           Tests:       T1 T2 T3 
40                      
41                        // opcode check
42         1/1            assign opcode_allowed = (tl_i.a_opcode == PutFullData)
           Tests:       T5 T6 T7 
43                                              | (tl_i.a_opcode == PutPartialData)
44                                              | (tl_i.a_opcode == Get);
45                      
46                        // a channel configuration check
47                        logic addr_sz_chk;    // address and size alignment check
48                        logic mask_chk;       // inactive lane a_mask check
49                        logic fulldata_chk;   // PutFullData should have size match to mask
50                      
51                        localparam bit [MW-1:0] MaskOne = 1;
52                        logic [MW-1:0] mask;
53                      
54         0/1     ==>    assign mask = MaskOne << tl_i.a_address[SubAW-1:0];
55                      
56                        always_comb begin
57         1/1              addr_sz_chk  = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              mask_chk     = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              fulldata_chk = 1'b0; // Only valid when opcode is PutFullData
           Tests:       T1 T2 T3 
60                      
61         1/1              if (tl_i.a_valid) begin
           Tests:       T1 T2 T3 
62         1/1                unique case (tl_i.a_size)
           Tests:       T5 T6 T7 
63                              'h0: begin // 1 Byte
64         excluded               addr_sz_chk  = 1'b1;
Exclude Annotation: VC_COV_UNR
65         excluded               mask_chk     = ~|(tl_i.a_mask & ~mask);
Exclude Annotation: VC_COV_UNR
66         excluded               fulldata_chk = |(tl_i.a_mask & mask);
Exclude Annotation: VC_COV_UNR
67                              end
68                      
69                              'h1: begin // 2 Byte
70         excluded               addr_sz_chk  = ~tl_i.a_address[0];
Exclude Annotation: VC_COV_UNR
71                                // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
72         excluded               mask_chk     = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
Exclude Annotation: VC_COV_UNR
73                                             : ~|(tl_i.a_mask & 4'b1100);
74         excluded               fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
Exclude Annotation: VC_COV_UNR
75                              end
76                      
77                              'h2: begin // 4 Byte
78         1/1                    addr_sz_chk  = ~|tl_i.a_address[SubAW-1:0];
           Tests:       T5 T6 T7 
79         1/1                    mask_chk     = 1'b1;
           Tests:       T5 T6 T7 
80         1/1                    fulldata_chk = &tl_i.a_mask[3:0];
           Tests:       T5 T6 T7 
81                              end
82                      
83                              default: begin // else
84                                addr_sz_chk  = 1'b0;
Exclude Annotation: VC_COV_UNR
85                                mask_chk     = 1'b0;
Exclude Annotation: VC_COV_UNR
86                                fulldata_chk = 1'b0;
Exclude Annotation: VC_COV_UNR
87                              end
88                            endcase
89                          end else begin
90         1/1                addr_sz_chk  = 1'b0;
           Tests:       T1 T2 T3 
91         1/1                mask_chk     = 1'b0;
           Tests:       T1 T2 T3 
92         1/1                fulldata_chk = 1'b0;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96         1/1            assign a_config_allowed = addr_sz_chk
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T5,T6,T7
0	0	1	Excluded		VC_COV_UNR
0	1	0	Excluded		VC_COV_UNR
1	0	0	Covered	T1,T2,T3

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Excluded		VC_COV_UNR
0	0	1	Covered	T5,T6,T7
0	1	0	Excluded		VC_COV_UNR
1	0	0	Covered	T5,T6,T7

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T5,T6,T7

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	1	0	Excluded		VC_COV_UNR
1	0	0	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	61	2	2	100.00

61             if (tl_i.a_valid) begin
               -1-  
62               unique case (tl_i.a_size)
                        -2-  
63                 'h0: begin // 1 Byte
64                   addr_sz_chk  = 1'b1;
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
65                   mask_chk     = ~|(tl_i.a_mask & ~mask);
66                   fulldata_chk = |(tl_i.a_mask & mask);
67                 end
68         
69                 'h1: begin // 2 Byte
70                   addr_sz_chk  = ~tl_i.a_address[0];
71                   // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
72                   mask_chk     = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
                                                        -3-  
                                                        ==> (Excluded)  
                                                        ==> (Excluded)  
73                                : ~|(tl_i.a_mask & 4'b1100);
74                   fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
                                                        -4-  
                                                        ==> (Excluded)  
                                                        ==> (Excluded)  
75                 end
76         
77                 'h2: begin // 4 Byte
78                   addr_sz_chk  = ~|tl_i.a_address[SubAW-1:0];
                     ==>
79                   mask_chk     = 1'b1;
80                   fulldata_chk = &tl_i.a_mask[3:0];
81                 end
82         
83                 default: begin // else
84                   addr_sz_chk  = 1'b0;
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
85                   mask_chk     = 1'b0;
86                   fulldata_chk = 1'b0;
87                 end
88               endcase
89             end else begin
90               addr_sz_chk  = 1'b0;
                 ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	'h0	-	-	Excluded		VC_COV_UNR
1	'h1	1	-	Excluded		VC_COV_UNR
1	'h1	0	-	Excluded		VC_COV_UNR
1	'h1	-	1	Excluded		VC_COV_UNR
1	'h1	-	0	Excluded		VC_COV_UNR
1	'h00000002	-	-	Covered	T5,T6,T7
1	default	-	-	Excluded		VC_COV_UNR
0	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1011	1011	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	57	17	17	100.00
CONT_ASSIGN	96	1	1	100.00

25                        logic op_full, op_partial, op_get;
26         1/1            assign op_full    = (tl_i.a_opcode == PutFullData);
           Tests:       T1 T2 T3 
27         1/1            assign op_partial = (tl_i.a_opcode == PutPartialData);
           Tests:       T1 T2 T3 
28         1/1            assign op_get     = (tl_i.a_opcode == Get);
           Tests:       T1 T2 T3 
29                      
30                        // An instruction type transaction cannot be write
31                        logic instr_wr_err;
32         1/1            assign instr_wr_err = prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) &
           Tests:       T1 T2 T3 
33                                              (op_full | op_partial);
34                      
35                        logic instr_type_err;
36         1/1            assign instr_type_err = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type);
           Tests:       T1 T2 T3 
37                      
38                        // Anything that doesn't fall into the permitted category, it raises an error
39         1/1            assign err_o = ~(opcode_allowed & a_config_allowed) | instr_wr_err | instr_type_err;
           Tests:       T1 T2 T3 
40                      
41                        // opcode check
42         1/1            assign opcode_allowed = (tl_i.a_opcode == PutFullData)
           Tests:       T1 T2 T3 
43                                              | (tl_i.a_opcode == PutPartialData)
44                                              | (tl_i.a_opcode == Get);
45                      
46                        // a channel configuration check
47                        logic addr_sz_chk;    // address and size alignment check
48                        logic mask_chk;       // inactive lane a_mask check
49                        logic fulldata_chk;   // PutFullData should have size match to mask
50                      
51                        localparam bit [MW-1:0] MaskOne = 1;
52                        logic [MW-1:0] mask;
53                      
54         1/1            assign mask = MaskOne << tl_i.a_address[SubAW-1:0];
           Tests:       T1 T2 T3 
55                      
56                        always_comb begin
57         1/1              addr_sz_chk  = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              mask_chk     = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              fulldata_chk = 1'b0; // Only valid when opcode is PutFullData
           Tests:       T1 T2 T3 
60                      
61         1/1              if (tl_i.a_valid) begin
           Tests:       T1 T2 T3 
62         1/1                unique case (tl_i.a_size)
           Tests:       T1 T2 T3 
63                              'h0: begin // 1 Byte
64         1/1                    addr_sz_chk  = 1'b1;
           Tests:       T1 T2 T3 
65         1/1                    mask_chk     = ~|(tl_i.a_mask & ~mask);
           Tests:       T1 T2 T3 
66         1/1                    fulldata_chk = |(tl_i.a_mask & mask);
           Tests:       T1 T2 T3 
67                              end
68                      
69                              'h1: begin // 2 Byte
70         1/1                    addr_sz_chk  = ~tl_i.a_address[0];
           Tests:       T1 T2 T3 
71                                // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
72         1/1                    mask_chk     = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
           Tests:       T1 T2 T3 
73                                             : ~|(tl_i.a_mask & 4'b1100);
74         1/1                    fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
           Tests:       T1 T2 T3 
75                              end
76                      
77                              'h2: begin // 4 Byte
78         1/1                    addr_sz_chk  = ~|tl_i.a_address[SubAW-1:0];
           Tests:       T1 T2 T3 
79         1/1                    mask_chk     = 1'b1;
           Tests:       T1 T2 T3 
80         1/1                    fulldata_chk = &tl_i.a_mask[3:0];
           Tests:       T1 T2 T3 
81                              end
82                      
83                              default: begin // else
84                                addr_sz_chk  = 1'b0;
85                                mask_chk     = 1'b0;
86                                fulldata_chk = 1'b0;
87                              end
88                            endcase
89                          end else begin
90         1/1                addr_sz_chk  = 1'b0;
           Tests:       T1 T2 T3 
91         1/1                mask_chk     = 1'b0;
           Tests:       T1 T2 T3 
92         1/1                fulldata_chk = 1'b0;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96         1/1            assign a_config_allowed = addr_sz_chk
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T93,T94,T95
0	1	0	Covered	T93,T94,T95
1	0	0	Covered	T5,T16,T6

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T114,T121,T125
1	0	Covered	T5,T16,T6
1	1	Covered	T1,T2,T3

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T148,T117,T99
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T95,T117,T163
1	0	1	Covered	T148,T152,T198
1	1	0	Covered	T117,T99,T208
1	1	1	Covered	T1,T2,T3

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T16,T6
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	61	8	8	100.00

61             if (tl_i.a_valid) begin
               -1-  
62               unique case (tl_i.a_size)
                        -2-  
63                 'h0: begin // 1 Byte
64                   addr_sz_chk  = 1'b1;
                     ==>
65                   mask_chk     = ~|(tl_i.a_mask & ~mask);
66                   fulldata_chk = |(tl_i.a_mask & mask);
67                 end
68         
69                 'h1: begin // 2 Byte
70                   addr_sz_chk  = ~tl_i.a_address[0];
71                   // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
72                   mask_chk     = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
                                                        -3-  
                                                        ==>  
                                                        ==>  
73                                : ~|(tl_i.a_mask & 4'b1100);
74                   fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
                                                        -4-  
                                                        ==>  
                                                        ==>  
75                 end
76         
77                 'h2: begin // 4 Byte
78                   addr_sz_chk  = ~|tl_i.a_address[SubAW-1:0];
                     ==>
79                   mask_chk     = 1'b1;
80                   fulldata_chk = &tl_i.a_mask[3:0];
81                 end
82         
83                 default: begin // else
84                   addr_sz_chk  = 1'b0;
                     ==>
85                   mask_chk     = 1'b0;
86                   fulldata_chk = 1'b0;
87                 end
88               endcase
89             end else begin
90               addr_sz_chk  = 1'b0;
                 ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T1,T2,T3
1	'h1	1	-	Covered	T2,T3,T4
1	'h1	0	-	Covered	T1,T2,T3
1	'h1	-	1	Covered	T2,T3,T4
1	'h1	-	0	Covered	T1,T2,T3
1	'h00000002	-	-	Covered	T1,T2,T3
1	default	-	-	Covered	T148,T198,T162
0	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1011	1011	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0