Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	829163	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1011903

1

T1

92

T2

7

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1557715	1			T1	91		T2	68		T3	2
values[0x0]	141359	1			T1	24		T2	4		T3	1
values[0x1]	141992	1			T1	39		T2	4		T4	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	655538	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1185528

1

T1

109

T2

28

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5142	1			T12	1		T18	1		T8	1
valid_sources[0x01]	20442	1			T4	2		T8	1		T20	5
valid_sources[0x02]	6723	1			T18	2		T8	7		T20	11
valid_sources[0x03]	5466	1			T18	2		T8	6		T20	23
valid_sources[0x04]	5299	1			T2	2		T4	5		T8	1
valid_sources[0x05]	4875	1			T12	2		T18	3		T8	1
valid_sources[0x06]	5073	1			T4	7		T18	2		T8	3
valid_sources[0x07]	7029	1			T18	2		T8	3		T20	1
valid_sources[0x08]	6106	1			T4	1		T18	1		T8	3
valid_sources[0x09]	5468	1			T18	1		T8	4		T24	5
valid_sources[0x0a]	4896	1			T18	1		T8	2		T24	8
valid_sources[0x0b]	5093	1			T12	3		T8	2		T20	1
valid_sources[0x0c]	4950	1			T12	1		T18	4		T8	3
valid_sources[0x0d]	5920	1			T12	1		T18	1		T8	2
valid_sources[0x0e]	4965	1			T12	1		T18	3		T8	1
valid_sources[0x0f]	4539	1			T4	2		T12	2		T18	2
valid_sources[0x10]	4714	1			T8	1		T20	3		T24	13
valid_sources[0x11]	4947	1			T12	3		T8	3		T24	5
valid_sources[0x12]	5789	1			T12	1		T18	2		T8	1
valid_sources[0x13]	6726	1			T8	2		T20	10		T24	11
valid_sources[0x14]	5376	1			T4	1		T8	3		T20	3
valid_sources[0x15]	4851	1			T12	2		T18	1		T20	10
valid_sources[0x16]	4842	1			T2	8		T12	1		T18	2
valid_sources[0x17]	4804	1			T12	1		T18	1		T8	3
valid_sources[0x18]	4804	1			T8	3		T20	6		T24	8
valid_sources[0x19]	4959	1			T4	5		T15	3		T18	2
valid_sources[0x1a]	5288	1			T12	1		T18	3		T8	1
valid_sources[0x1b]	4976	1			T4	1		T18	3		T20	5
valid_sources[0x1c]	5029	1			T12	3		T8	2		T24	5
valid_sources[0x1d]	5113	1			T4	2		T12	1		T8	1
valid_sources[0x1e]	5531	1			T4	4		T18	3		T8	3
valid_sources[0x1f]	4811	1			T4	5		T12	1		T18	1
valid_sources[0x20]	4773	1			T12	1		T18	2		T20	27
valid_sources[0x21]	9163	1			T4	2		T18	1		T8	1
valid_sources[0x22]	5706	1			T12	3		T18	1		T8	3
valid_sources[0x23]	15951	1			T4	5		T12	1		T18	2
valid_sources[0x24]	206383	1			T4	1		T12	2		T18	2
valid_sources[0x25]	5017	1			T18	3		T8	4		T20	8
valid_sources[0x26]	5374	1			T12	4		T18	1		T8	3
valid_sources[0x27]	5156	1			T2	9		T12	2		T18	3
valid_sources[0x28]	5711	1			T4	2		T12	2		T18	2
valid_sources[0x29]	6857	1			T4	5		T12	3		T18	1
valid_sources[0x2a]	4762	1			T4	6		T18	2		T20	8
valid_sources[0x2b]	5917	1			T4	1		T18	2		T8	1
valid_sources[0x2c]	5448	1			T4	1		T18	2		T8	3
valid_sources[0x2d]	58462	1			T4	2		T18	2		T8	2
valid_sources[0x2e]	6124	1			T4	1		T18	1		T8	5
valid_sources[0x2f]	4968	1			T4	5		T12	2		T8	2
valid_sources[0x30]	4907	1			T4	4		T15	1		T18	1
valid_sources[0x31]	4566	1			T4	1		T12	1		T18	2
valid_sources[0x32]	4958	1			T12	2		T18	1		T8	4
valid_sources[0x33]	5742	1			T12	2		T18	1		T8	1
valid_sources[0x34]	4739	1			T4	6		T12	3		T8	2
valid_sources[0x35]	4846	1			T12	1		T18	3		T8	4
valid_sources[0x36]	4998	1			T2	3		T4	3		T12	1
valid_sources[0x37]	5824	1			T8	4		T24	6		T21	17
valid_sources[0x38]	5188	1			T4	4		T12	2		T8	3
valid_sources[0x39]	5455	1			T4	6		T12	1		T18	1
valid_sources[0x3a]	6272	1			T4	1		T12	1		T18	1
valid_sources[0x3b]	4894	1			T4	4		T12	1		T18	3
valid_sources[0x3c]	5104	1			T4	1		T12	1		T18	2
valid_sources[0x3d]	5714	1			T4	4		T12	2		T18	2
valid_sources[0x3e]	4684	1			T4	1		T12	4		T18	2
valid_sources[0x3f]	12811	1			T4	2		T12	1		T8	1
valid_sources[0x40]	5058	1			T12	3		T18	5		T8	1
valid_sources[0x41]	4836	1			T4	1		T12	1		T18	1
valid_sources[0x42]	5177	1			T4	2		T12	1		T15	1
valid_sources[0x43]	5165	1			T2	2		T18	2		T8	1
valid_sources[0x44]	8815	1			T4	2		T12	1		T18	1
valid_sources[0x45]	8138	1			T12	1		T8	2		T24	5
valid_sources[0x46]	5285	1			T18	1		T8	2		T24	3
valid_sources[0x47]	5079	1			T18	1		T8	1		T20	9
valid_sources[0x48]	6095	1			T4	1		T18	1		T8	1
valid_sources[0x49]	7961	1			T12	1		T18	3		T8	1
valid_sources[0x4a]	9875	1			T12	1		T18	1		T8	3
valid_sources[0x4b]	5521	1			T4	2		T18	1		T8	3
valid_sources[0x4c]	6216	1			T12	1		T18	2		T8	9
valid_sources[0x4d]	5031	1			T12	2		T18	5		T8	2
valid_sources[0x4e]	6374	1			T12	1		T15	1		T8	2
valid_sources[0x4f]	4988	1			T12	2		T8	1		T20	1
valid_sources[0x50]	5181	1			T4	1		T18	1		T8	1
valid_sources[0x51]	6418	1			T18	4		T8	3		T20	28
valid_sources[0x52]	29621	1			T4	4		T12	1		T18	1
valid_sources[0x53]	18605	1			T4	1		T18	5		T8	1
valid_sources[0x54]	6351	1			T4	1		T12	2		T18	1
valid_sources[0x55]	6474	1			T4	4		T12	2		T18	2
valid_sources[0x56]	6509	1			T12	1		T18	1		T8	1
valid_sources[0x57]	5735	1			T4	2		T18	3		T8	2
valid_sources[0x58]	5069	1			T4	2		T8	2		T24	14
valid_sources[0x59]	7720	1			T12	1		T13	1131		T18	1
valid_sources[0x5a]	4945	1			T8	2		T24	2		T16	11
valid_sources[0x5b]	5173	1			T8	2		T24	8		T16	8
valid_sources[0x5c]	4704	1			T2	14		T4	2		T12	2
valid_sources[0x5d]	5012	1			T12	1		T8	4		T20	1
valid_sources[0x5e]	4685	1			T4	3		T18	1		T8	1
valid_sources[0x5f]	6026	1			T18	2		T8	1		T20	2
valid_sources[0x60]	4870	1			T2	1		T18	1		T8	2
valid_sources[0x61]	4796	1			T12	1		T14	5		T8	3
valid_sources[0x62]	4892	1			T12	1		T18	2		T8	1
valid_sources[0x63]	5311	1			T12	3		T18	1		T8	5
valid_sources[0x64]	7212	1			T4	1		T12	2		T8	3
valid_sources[0x65]	4750	1			T8	1		T20	9		T24	14
valid_sources[0x66]	8320	1			T18	1		T8	1		T20	17
valid_sources[0x67]	4866	1			T18	2		T8	3		T20	1
valid_sources[0x68]	4808	1			T18	2		T8	2		T24	4
valid_sources[0x69]	5415	1			T12	1		T18	2		T8	3
valid_sources[0x6a]	4854	1			T12	4		T18	1		T8	4
valid_sources[0x6b]	6911	1			T4	2		T12	1		T18	2
valid_sources[0x6c]	6361	1			T2	1		T3	2		T12	4
valid_sources[0x6d]	5195	1			T4	2		T18	1		T8	3
valid_sources[0x6e]	4760	1			T4	1		T18	1		T24	9
valid_sources[0x6f]	9576	1			T12	1		T15	1		T18	2
valid_sources[0x70]	4962	1			T4	1		T18	3		T20	2
valid_sources[0x71]	4704	1			T4	2		T12	2		T15	1
valid_sources[0x72]	4737	1			T4	1		T12	2		T18	2
valid_sources[0x73]	6112	1			T12	1		T18	3		T8	2
valid_sources[0x74]	5047	1			T18	1		T8	2		T24	7
valid_sources[0x75]	7933	1			T12	1		T18	1		T8	2
valid_sources[0x76]	5409	1			T4	1		T12	1		T18	1
valid_sources[0x77]	4863	1			T12	2		T18	2		T8	1
valid_sources[0x78]	4692	1			T12	2		T18	2		T8	6
valid_sources[0x79]	5909	1			T18	1		T24	12		T16	8
valid_sources[0x7a]	5120	1			T4	1		T15	1		T18	3
valid_sources[0x7b]	4804	1			T4	3		T18	2		T8	2
valid_sources[0x7c]	4870	1			T12	1		T15	1		T24	15
valid_sources[0x7d]	5536	1			T4	1		T12	3		T18	1
valid_sources[0x7e]	5002	1			T4	1		T12	2		T8	1
valid_sources[0x7f]	4841	1			T2	2		T4	2		T12	1
valid_sources[0x80]	4882	1			T4	4		T18	2		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

768749

1

T1

42

T4

95

T12

61

values[0x0]

all_enables

biggest_size

122235

1

T1

21

T2

3

T3

1

values[0x1]

all_enables

biggest_size

120919

1

T1

29

T2

4

T4

41