Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	54140188	15658	0	0
claim_transition_if_regwen_rd_A	54140188	1912	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54140188	15658	0	0
T17	174653	2	0	0
T25	40140	0	0	0
T40	20971	0	0	0
T41	27065	0	0	0
T49	25911	0	0	0
T66	44499	0	0	0
T67	9136	0	0	0
T90	24490	0	0	0
T97	2254	0	0	0
T99	0	5	0	0
T100	0	15	0	0
T105	1375	0	0	0
T152	0	5	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	8	0	0
T158	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54140188	1912	0	0
T78	2049	0	0	0
T118	0	30	0	0
T120	0	42	0	0
T133	0	16	0	0
T159	283552	9	0	0
T160	0	21	0	0
T161	0	14	0	0
T162	0	2	0	0
T163	0	9	0	0
T164	0	4	0	0
T165	0	241	0	0
T166	330659	0	0	0
T167	7439	0	0	0
T168	25444	0	0	0
T169	24699	0	0	0
T170	30432	0	0	0
T171	67186	0	0	0
T172	1579	0	0	0
T173	5650	0	0	0