| T358 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.1573877668 |
|
|
Oct 09 10:51:56 AM UTC 24 |
Oct 09 10:52:03 AM UTC 24 |
86565167 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.1476273383 |
|
|
Oct 09 10:51:46 AM UTC 24 |
Oct 09 10:52:04 AM UTC 24 |
81764422 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.1488164771 |
|
|
Oct 09 10:51:58 AM UTC 24 |
Oct 09 10:52:04 AM UTC 24 |
88562542 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.138281697 |
|
|
Oct 09 10:51:51 AM UTC 24 |
Oct 09 10:52:05 AM UTC 24 |
287861191 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.886366498 |
|
|
Oct 09 10:51:59 AM UTC 24 |
Oct 09 10:52:05 AM UTC 24 |
314227878 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.478594659 |
|
|
Oct 09 10:52:01 AM UTC 24 |
Oct 09 10:52:07 AM UTC 24 |
100042342 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.3127632405 |
|
|
Oct 09 10:52:06 AM UTC 24 |
Oct 09 10:52:08 AM UTC 24 |
195423186 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.920565184 |
|
|
Oct 09 10:52:07 AM UTC 24 |
Oct 09 10:52:09 AM UTC 24 |
54726691 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.546365094 |
|
|
Oct 09 10:51:48 AM UTC 24 |
Oct 09 10:52:11 AM UTC 24 |
566752257 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.31525275 |
|
|
Oct 09 10:51:51 AM UTC 24 |
Oct 09 10:52:13 AM UTC 24 |
7819317783 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.510373070 |
|
|
Oct 09 10:51:46 AM UTC 24 |
Oct 09 10:52:13 AM UTC 24 |
356659112 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.1428229610 |
|
|
Oct 09 10:51:58 AM UTC 24 |
Oct 09 10:52:13 AM UTC 24 |
164265827 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.3363751237 |
|
|
Oct 09 10:52:06 AM UTC 24 |
Oct 09 10:52:13 AM UTC 24 |
632505125 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.1425806304 |
|
|
Oct 09 10:51:46 AM UTC 24 |
Oct 09 10:52:13 AM UTC 24 |
2003808644 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.1530760365 |
|
|
Oct 09 10:52:04 AM UTC 24 |
Oct 09 10:52:14 AM UTC 24 |
256388045 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.589260753 |
|
|
Oct 09 10:51:51 AM UTC 24 |
Oct 09 10:52:14 AM UTC 24 |
2482984210 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.2346423568 |
|
|
Oct 09 10:52:02 AM UTC 24 |
Oct 09 10:52:17 AM UTC 24 |
552299460 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.2900889521 |
|
|
Oct 09 10:52:09 AM UTC 24 |
Oct 09 10:52:17 AM UTC 24 |
287384529 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.255796856 |
|
|
Oct 09 10:48:52 AM UTC 24 |
Oct 09 10:52:18 AM UTC 24 |
7578387946 ps |
| T35 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.2671442272 |
|
|
Oct 09 10:52:02 AM UTC 24 |
Oct 09 10:52:18 AM UTC 24 |
403570609 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.804200051 |
|
|
Oct 09 10:52:09 AM UTC 24 |
Oct 09 10:52:19 AM UTC 24 |
440995957 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.2243245337 |
|
|
Oct 09 10:52:00 AM UTC 24 |
Oct 09 10:52:20 AM UTC 24 |
5674778507 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.3345125122 |
|
|
Oct 09 10:51:59 AM UTC 24 |
Oct 09 10:52:20 AM UTC 24 |
397350363 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.1948479888 |
|
|
Oct 09 10:51:13 AM UTC 24 |
Oct 09 10:52:21 AM UTC 24 |
1307483780 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.424426354 |
|
|
Oct 09 10:52:04 AM UTC 24 |
Oct 09 10:52:22 AM UTC 24 |
1474373557 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2180376940 |
|
|
Oct 09 10:52:20 AM UTC 24 |
Oct 09 10:52:23 AM UTC 24 |
78865775 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.3622055112 |
|
|
Oct 09 10:52:14 AM UTC 24 |
Oct 09 10:52:23 AM UTC 24 |
1775943042 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1779986608 |
|
|
Oct 09 10:52:21 AM UTC 24 |
Oct 09 10:52:24 AM UTC 24 |
13386462 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.1797520987 |
|
|
Oct 09 10:52:16 AM UTC 24 |
Oct 09 10:52:24 AM UTC 24 |
857604517 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.3159101653 |
|
|
Oct 09 10:51:37 AM UTC 24 |
Oct 09 10:52:25 AM UTC 24 |
13297823719 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.4236829209 |
|
|
Oct 09 10:52:21 AM UTC 24 |
Oct 09 10:52:28 AM UTC 24 |
442128853 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.2775114692 |
|
|
Oct 09 10:52:14 AM UTC 24 |
Oct 09 10:52:28 AM UTC 24 |
4823303764 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.2164337552 |
|
|
Oct 09 10:52:12 AM UTC 24 |
Oct 09 10:52:29 AM UTC 24 |
319510809 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.4208884007 |
|
|
Oct 09 10:52:10 AM UTC 24 |
Oct 09 10:52:29 AM UTC 24 |
1249499915 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.977804442 |
|
|
Oct 09 10:52:14 AM UTC 24 |
Oct 09 10:52:29 AM UTC 24 |
276711842 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.1353378558 |
|
|
Oct 09 10:51:55 AM UTC 24 |
Oct 09 10:52:29 AM UTC 24 |
889427846 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.2670295759 |
|
|
Oct 09 10:52:24 AM UTC 24 |
Oct 09 10:52:31 AM UTC 24 |
368919464 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.810744927 |
|
|
Oct 09 10:52:01 AM UTC 24 |
Oct 09 10:52:32 AM UTC 24 |
1428103942 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.2217487243 |
|
|
Oct 09 10:52:25 AM UTC 24 |
Oct 09 10:52:33 AM UTC 24 |
362222975 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.997168382 |
|
|
Oct 09 10:52:18 AM UTC 24 |
Oct 09 10:52:34 AM UTC 24 |
1432643642 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.32876857 |
|
|
Oct 09 10:52:24 AM UTC 24 |
Oct 09 10:52:35 AM UTC 24 |
95008278 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.3338490292 |
|
|
Oct 09 10:52:58 AM UTC 24 |
Oct 09 10:53:02 AM UTC 24 |
138949674 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3119534949 |
|
|
Oct 09 10:52:18 AM UTC 24 |
Oct 09 10:52:36 AM UTC 24 |
510258767 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.3259722839 |
|
|
Oct 09 10:52:08 AM UTC 24 |
Oct 09 10:52:37 AM UTC 24 |
210122443 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.4153293811 |
|
|
Oct 09 10:52:16 AM UTC 24 |
Oct 09 10:52:38 AM UTC 24 |
361638733 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.1384459178 |
|
|
Oct 09 10:52:36 AM UTC 24 |
Oct 09 10:52:39 AM UTC 24 |
69613580 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1253491153 |
|
|
Oct 09 10:52:37 AM UTC 24 |
Oct 09 10:52:40 AM UTC 24 |
22800320 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.3703830765 |
|
|
Oct 09 10:52:36 AM UTC 24 |
Oct 09 10:52:40 AM UTC 24 |
26421201 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.4166836523 |
|
|
Oct 09 10:52:24 AM UTC 24 |
Oct 09 10:52:40 AM UTC 24 |
1389019776 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.1380475002 |
|
|
Oct 09 10:52:31 AM UTC 24 |
Oct 09 10:52:41 AM UTC 24 |
1626111117 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.1317451337 |
|
|
Oct 09 10:52:31 AM UTC 24 |
Oct 09 10:52:43 AM UTC 24 |
611497939 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.3373887703 |
|
|
Oct 09 10:52:32 AM UTC 24 |
Oct 09 10:52:44 AM UTC 24 |
1008361810 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.2976288677 |
|
|
Oct 09 10:51:23 AM UTC 24 |
Oct 09 10:52:45 AM UTC 24 |
7465460589 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.1768101346 |
|
|
Oct 09 10:52:40 AM UTC 24 |
Oct 09 10:52:45 AM UTC 24 |
192958977 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.2947720433 |
|
|
Oct 09 10:52:25 AM UTC 24 |
Oct 09 10:52:46 AM UTC 24 |
382406739 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.3149232849 |
|
|
Oct 09 10:51:04 AM UTC 24 |
Oct 09 10:52:47 AM UTC 24 |
7923933908 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2279982069 |
|
|
Oct 09 10:52:06 AM UTC 24 |
Oct 09 10:52:47 AM UTC 24 |
4803260319 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.2659803918 |
|
|
Oct 09 10:52:31 AM UTC 24 |
Oct 09 10:52:48 AM UTC 24 |
1680006407 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.3466679323 |
|
|
Oct 09 10:52:39 AM UTC 24 |
Oct 09 10:52:49 AM UTC 24 |
74931667 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.4063724753 |
|
|
Oct 09 10:52:31 AM UTC 24 |
Oct 09 10:52:50 AM UTC 24 |
299557428 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.2282488762 |
|
|
Oct 09 10:52:41 AM UTC 24 |
Oct 09 10:52:51 AM UTC 24 |
1570187705 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.3515108782 |
|
|
Oct 09 10:52:50 AM UTC 24 |
Oct 09 10:52:53 AM UTC 24 |
27270650 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.3171274721 |
|
|
Oct 09 10:52:29 AM UTC 24 |
Oct 09 10:52:54 AM UTC 24 |
2733661254 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.1724014334 |
|
|
Oct 09 10:52:51 AM UTC 24 |
Oct 09 10:52:54 AM UTC 24 |
18331776 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1817383464 |
|
|
Oct 09 10:52:52 AM UTC 24 |
Oct 09 10:52:55 AM UTC 24 |
43662268 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.2504394084 |
|
|
Oct 09 10:51:34 AM UTC 24 |
Oct 09 10:52:55 AM UTC 24 |
1742926699 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.4261968992 |
|
|
Oct 09 10:52:40 AM UTC 24 |
Oct 09 10:52:56 AM UTC 24 |
424939562 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.2031901285 |
|
|
Oct 09 10:52:47 AM UTC 24 |
Oct 09 10:53:03 AM UTC 24 |
1285722651 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.641623842 |
|
|
Oct 09 10:52:55 AM UTC 24 |
Oct 09 10:53:03 AM UTC 24 |
117871761 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.3631412060 |
|
|
Oct 09 10:52:22 AM UTC 24 |
Oct 09 10:53:03 AM UTC 24 |
172708391 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.1802039717 |
|
|
Oct 09 10:52:49 AM UTC 24 |
Oct 09 10:53:03 AM UTC 24 |
1376786310 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.850216691 |
|
|
Oct 09 10:52:43 AM UTC 24 |
Oct 09 10:53:05 AM UTC 24 |
858092466 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.253270336 |
|
|
Oct 09 10:52:31 AM UTC 24 |
Oct 09 10:53:05 AM UTC 24 |
2157578725 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.1030154960 |
|
|
Oct 09 10:52:57 AM UTC 24 |
Oct 09 10:53:05 AM UTC 24 |
1010545387 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.1896920812 |
|
|
Oct 09 10:52:55 AM UTC 24 |
Oct 09 10:53:07 AM UTC 24 |
54250329 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.601900864 |
|
|
Oct 09 10:52:56 AM UTC 24 |
Oct 09 10:53:07 AM UTC 24 |
420173854 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2679386879 |
|
|
Oct 09 10:51:48 AM UTC 24 |
Oct 09 10:53:07 AM UTC 24 |
7189850924 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.2942676129 |
|
|
Oct 09 10:52:27 AM UTC 24 |
Oct 09 10:53:08 AM UTC 24 |
5127034372 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.954050756 |
|
|
Oct 09 10:52:47 AM UTC 24 |
Oct 09 10:53:08 AM UTC 24 |
615807136 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.2820788513 |
|
|
Oct 09 10:52:37 AM UTC 24 |
Oct 09 10:53:09 AM UTC 24 |
951713311 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.1448052165 |
|
|
Oct 09 10:51:59 AM UTC 24 |
Oct 09 10:53:10 AM UTC 24 |
2582301978 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.989922725 |
|
|
Oct 09 10:52:49 AM UTC 24 |
Oct 09 10:53:10 AM UTC 24 |
2143010481 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.3411702994 |
|
|
Oct 09 10:53:07 AM UTC 24 |
Oct 09 10:53:10 AM UTC 24 |
21653366 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.295292601 |
|
|
Oct 09 10:53:08 AM UTC 24 |
Oct 09 10:53:11 AM UTC 24 |
12998908 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.2672880257 |
|
|
Oct 09 10:53:10 AM UTC 24 |
Oct 09 10:53:13 AM UTC 24 |
120331667 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.973639787 |
|
|
Oct 09 10:49:52 AM UTC 24 |
Oct 09 10:53:14 AM UTC 24 |
41677354430 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.3070108984 |
|
|
Oct 09 10:52:56 AM UTC 24 |
Oct 09 10:53:15 AM UTC 24 |
2750492941 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.306000828 |
|
|
Oct 09 10:52:58 AM UTC 24 |
Oct 09 10:53:17 AM UTC 24 |
391514067 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.3201731780 |
|
|
Oct 09 10:53:11 AM UTC 24 |
Oct 09 10:53:17 AM UTC 24 |
117475026 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.1814215797 |
|
|
Oct 09 10:53:08 AM UTC 24 |
Oct 09 10:53:17 AM UTC 24 |
82415305 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.2518147882 |
|
|
Oct 09 10:53:10 AM UTC 24 |
Oct 09 10:53:19 AM UTC 24 |
123303564 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.862239347 |
|
|
Oct 09 10:53:14 AM UTC 24 |
Oct 09 10:53:19 AM UTC 24 |
131525902 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.3152430704 |
|
|
Oct 09 10:53:04 AM UTC 24 |
Oct 09 10:53:19 AM UTC 24 |
724329444 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.4004858696 |
|
|
Oct 09 10:53:05 AM UTC 24 |
Oct 09 10:53:21 AM UTC 24 |
249378548 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.3059907370 |
|
|
Oct 09 10:53:21 AM UTC 24 |
Oct 09 10:53:24 AM UTC 24 |
27785193 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.1446121674 |
|
|
Oct 09 10:53:04 AM UTC 24 |
Oct 09 10:53:26 AM UTC 24 |
1462523920 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.351743051 |
|
|
Oct 09 10:53:11 AM UTC 24 |
Oct 09 10:53:26 AM UTC 24 |
1245949273 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1267075663 |
|
|
Oct 09 10:53:23 AM UTC 24 |
Oct 09 10:53:26 AM UTC 24 |
25736980 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1738437057 |
|
|
Oct 09 10:52:50 AM UTC 24 |
Oct 09 10:53:29 AM UTC 24 |
6399014125 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1699324970 |
|
|
Oct 09 10:53:26 AM UTC 24 |
Oct 09 10:53:29 AM UTC 24 |
16500785 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.3470703268 |
|
|
Oct 09 10:52:45 AM UTC 24 |
Oct 09 10:53:30 AM UTC 24 |
2445611039 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.1517319784 |
|
|
Oct 09 10:52:44 AM UTC 24 |
Oct 09 10:53:30 AM UTC 24 |
5028718090 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.3058021820 |
|
|
Oct 09 10:52:16 AM UTC 24 |
Oct 09 10:54:03 AM UTC 24 |
3536435546 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.1130784532 |
|
|
Oct 09 10:53:13 AM UTC 24 |
Oct 09 10:53:31 AM UTC 24 |
998968051 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.2268840659 |
|
|
Oct 09 10:53:18 AM UTC 24 |
Oct 09 10:53:32 AM UTC 24 |
230847632 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.2206406060 |
|
|
Oct 09 10:52:14 AM UTC 24 |
Oct 09 10:53:33 AM UTC 24 |
1967772916 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.2681977158 |
|
|
Oct 09 10:53:18 AM UTC 24 |
Oct 09 10:53:33 AM UTC 24 |
421343756 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.3453768330 |
|
|
Oct 09 10:51:41 AM UTC 24 |
Oct 09 10:53:33 AM UTC 24 |
10164045687 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.2633119948 |
|
|
Oct 09 10:52:55 AM UTC 24 |
Oct 09 10:53:33 AM UTC 24 |
577274238 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.939569260 |
|
|
Oct 09 10:53:28 AM UTC 24 |
Oct 09 10:53:33 AM UTC 24 |
136772933 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.3945223196 |
|
|
Oct 09 10:53:11 AM UTC 24 |
Oct 09 10:53:34 AM UTC 24 |
1255099521 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.4266329965 |
|
|
Oct 09 10:53:05 AM UTC 24 |
Oct 09 10:53:34 AM UTC 24 |
2105999393 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.539545192 |
|
|
Oct 09 10:53:18 AM UTC 24 |
Oct 09 10:53:35 AM UTC 24 |
1142211825 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.1776330432 |
|
|
Oct 09 10:53:32 AM UTC 24 |
Oct 09 10:53:35 AM UTC 24 |
235310364 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.170750468 |
|
|
Oct 09 10:53:10 AM UTC 24 |
Oct 09 10:53:37 AM UTC 24 |
645486206 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.216100713 |
|
|
Oct 09 10:53:28 AM UTC 24 |
Oct 09 10:53:38 AM UTC 24 |
276870901 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.1078616732 |
|
|
Oct 09 10:53:34 AM UTC 24 |
Oct 09 10:53:39 AM UTC 24 |
300157607 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.909308803 |
|
|
Oct 09 10:53:37 AM UTC 24 |
Oct 09 10:53:39 AM UTC 24 |
19607342 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3194161617 |
|
|
Oct 09 10:53:37 AM UTC 24 |
Oct 09 10:53:39 AM UTC 24 |
14352292 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3048660693 |
|
|
Oct 09 10:53:30 AM UTC 24 |
Oct 09 10:53:40 AM UTC 24 |
190007041 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.2928043995 |
|
|
Oct 09 10:53:37 AM UTC 24 |
Oct 09 10:53:43 AM UTC 24 |
121850698 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.2169088967 |
|
|
Oct 09 10:53:34 AM UTC 24 |
Oct 09 10:53:43 AM UTC 24 |
366226651 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.1726691259 |
|
|
Oct 09 10:53:39 AM UTC 24 |
Oct 09 10:53:44 AM UTC 24 |
173718481 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.898746218 |
|
|
Oct 09 10:53:55 AM UTC 24 |
Oct 09 10:54:03 AM UTC 24 |
288505125 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.1058208832 |
|
|
Oct 09 10:53:11 AM UTC 24 |
Oct 09 10:53:45 AM UTC 24 |
1707000975 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.273626725 |
|
|
Oct 09 10:53:30 AM UTC 24 |
Oct 09 10:53:45 AM UTC 24 |
739677873 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.3884547844 |
|
|
Oct 09 10:53:36 AM UTC 24 |
Oct 09 10:53:49 AM UTC 24 |
396051911 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.2851811526 |
|
|
Oct 09 10:53:36 AM UTC 24 |
Oct 09 10:53:50 AM UTC 24 |
315700994 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.49156147 |
|
|
Oct 09 10:53:16 AM UTC 24 |
Oct 09 10:53:50 AM UTC 24 |
1104464101 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.3208755903 |
|
|
Oct 09 10:53:33 AM UTC 24 |
Oct 09 10:53:52 AM UTC 24 |
417702425 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3496745778 |
|
|
Oct 09 10:53:16 AM UTC 24 |
Oct 09 10:53:53 AM UTC 24 |
2341271465 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.313883947 |
|
|
Oct 09 10:53:38 AM UTC 24 |
Oct 09 10:53:53 AM UTC 24 |
423232276 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.2073082492 |
|
|
Oct 09 10:53:36 AM UTC 24 |
Oct 09 10:53:54 AM UTC 24 |
6340490109 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.2495431611 |
|
|
Oct 09 10:53:52 AM UTC 24 |
Oct 09 10:53:54 AM UTC 24 |
22431853 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.4081084284 |
|
|
Oct 09 10:52:58 AM UTC 24 |
Oct 09 10:53:55 AM UTC 24 |
23697849512 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.4243255338 |
|
|
Oct 09 10:53:46 AM UTC 24 |
Oct 09 10:53:55 AM UTC 24 |
300741011 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.4269681108 |
|
|
Oct 09 10:53:53 AM UTC 24 |
Oct 09 10:53:56 AM UTC 24 |
42426518 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.2996494772 |
|
|
Oct 09 10:53:27 AM UTC 24 |
Oct 09 10:53:56 AM UTC 24 |
646394129 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.1559160059 |
|
|
Oct 09 10:53:52 AM UTC 24 |
Oct 09 10:53:56 AM UTC 24 |
218224492 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.3944986822 |
|
|
Oct 09 10:53:41 AM UTC 24 |
Oct 09 10:53:56 AM UTC 24 |
523439330 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.1802319069 |
|
|
Oct 09 10:53:41 AM UTC 24 |
Oct 09 10:53:59 AM UTC 24 |
859128575 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.3652496408 |
|
|
Oct 09 10:53:38 AM UTC 24 |
Oct 09 10:53:59 AM UTC 24 |
193968113 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.1936832934 |
|
|
Oct 09 10:53:44 AM UTC 24 |
Oct 09 10:53:59 AM UTC 24 |
741353611 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.787879654 |
|
|
Oct 09 10:53:41 AM UTC 24 |
Oct 09 10:54:00 AM UTC 24 |
3411171241 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.3943451653 |
|
|
Oct 09 10:53:48 AM UTC 24 |
Oct 09 10:54:02 AM UTC 24 |
329175722 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.2307425305 |
|
|
Oct 09 10:53:59 AM UTC 24 |
Oct 09 10:54:02 AM UTC 24 |
89904328 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2004895829 |
|
|
Oct 09 10:54:01 AM UTC 24 |
Oct 09 10:54:03 AM UTC 24 |
35043361 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.2346736178 |
|
|
Oct 09 10:51:50 AM UTC 24 |
Oct 09 10:54:04 AM UTC 24 |
64617059266 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.4139771476 |
|
|
Oct 09 10:54:01 AM UTC 24 |
Oct 09 10:54:05 AM UTC 24 |
165307545 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.3858877756 |
|
|
Oct 09 10:53:46 AM UTC 24 |
Oct 09 10:54:06 AM UTC 24 |
1374257287 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.3981422837 |
|
|
Oct 09 10:53:58 AM UTC 24 |
Oct 09 10:54:06 AM UTC 24 |
459192176 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.1903866982 |
|
|
Oct 09 10:53:55 AM UTC 24 |
Oct 09 10:54:06 AM UTC 24 |
95889062 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.861027298 |
|
|
Oct 09 10:52:42 AM UTC 24 |
Oct 09 10:54:06 AM UTC 24 |
1284529747 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.3356962642 |
|
|
Oct 09 10:53:55 AM UTC 24 |
Oct 09 10:54:07 AM UTC 24 |
432342072 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.170186681 |
|
|
Oct 09 10:54:03 AM UTC 24 |
Oct 09 10:54:07 AM UTC 24 |
50446710 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.1080823643 |
|
|
Oct 09 10:53:58 AM UTC 24 |
Oct 09 10:54:09 AM UTC 24 |
260398361 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.2498527941 |
|
|
Oct 09 10:54:07 AM UTC 24 |
Oct 09 10:54:10 AM UTC 24 |
58163352 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2334972252 |
|
|
Oct 09 10:54:09 AM UTC 24 |
Oct 09 10:54:11 AM UTC 24 |
14121701 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.2866963976 |
|
|
Oct 09 10:53:50 AM UTC 24 |
Oct 09 10:54:13 AM UTC 24 |
487570910 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.531757135 |
|
|
Oct 09 10:53:46 AM UTC 24 |
Oct 09 10:54:13 AM UTC 24 |
2953995769 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.4090651572 |
|
|
Oct 09 10:54:09 AM UTC 24 |
Oct 09 10:54:14 AM UTC 24 |
157190687 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.4090858325 |
|
|
Oct 09 10:54:04 AM UTC 24 |
Oct 09 10:54:15 AM UTC 24 |
1435203004 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3216038217 |
|
|
Oct 09 10:54:01 AM UTC 24 |
Oct 09 10:54:15 AM UTC 24 |
260703403 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.1411386769 |
|
|
Oct 09 10:54:11 AM UTC 24 |
Oct 09 10:54:16 AM UTC 24 |
58164524 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.4239576024 |
|
|
Oct 09 10:53:58 AM UTC 24 |
Oct 09 10:54:16 AM UTC 24 |
1024753553 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.2557991452 |
|
|
Oct 09 10:54:11 AM UTC 24 |
Oct 09 10:54:17 AM UTC 24 |
304793024 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.3972752749 |
|
|
Oct 09 10:54:03 AM UTC 24 |
Oct 09 10:54:18 AM UTC 24 |
724122927 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.3150642653 |
|
|
Oct 09 10:54:06 AM UTC 24 |
Oct 09 10:54:19 AM UTC 24 |
316780643 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1499383762 |
|
|
Oct 09 10:53:57 AM UTC 24 |
Oct 09 10:54:20 AM UTC 24 |
375197052 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.2839595481 |
|
|
Oct 09 10:54:14 AM UTC 24 |
Oct 09 10:54:20 AM UTC 24 |
701268131 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.2470423355 |
|
|
Oct 09 10:54:04 AM UTC 24 |
Oct 09 10:54:20 AM UTC 24 |
5202572055 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.852958662 |
|
|
Oct 09 10:54:18 AM UTC 24 |
Oct 09 10:54:20 AM UTC 24 |
73825913 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1457702656 |
|
|
Oct 09 10:53:58 AM UTC 24 |
Oct 09 10:54:23 AM UTC 24 |
426927152 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.1829923889 |
|
|
Oct 09 10:53:34 AM UTC 24 |
Oct 09 10:54:23 AM UTC 24 |
4360198359 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.2749336737 |
|
|
Oct 09 10:54:19 AM UTC 24 |
Oct 09 10:54:23 AM UTC 24 |
130898636 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3574007874 |
|
|
Oct 09 10:54:21 AM UTC 24 |
Oct 09 10:54:24 AM UTC 24 |
12070997 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3324662778 |
|
|
Oct 09 10:53:05 AM UTC 24 |
Oct 09 10:54:25 AM UTC 24 |
7288431593 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.3592625601 |
|
|
Oct 09 10:53:55 AM UTC 24 |
Oct 09 10:54:25 AM UTC 24 |
638092178 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.3994640751 |
|
|
Oct 09 10:54:16 AM UTC 24 |
Oct 09 10:54:25 AM UTC 24 |
914246484 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.3321163198 |
|
|
Oct 09 10:54:14 AM UTC 24 |
Oct 09 10:54:25 AM UTC 24 |
607060432 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2051767371 |
|
|
Oct 09 10:53:20 AM UTC 24 |
Oct 09 10:54:25 AM UTC 24 |
3383454166 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.1359589806 |
|
|
Oct 09 10:54:22 AM UTC 24 |
Oct 09 10:54:26 AM UTC 24 |
50120910 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.3814073872 |
|
|
Oct 09 10:53:04 AM UTC 24 |
Oct 09 10:54:26 AM UTC 24 |
15631419066 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.3719331980 |
|
|
Oct 09 10:54:47 AM UTC 24 |
Oct 09 10:54:51 AM UTC 24 |
70521236 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.4290655951 |
|
|
Oct 09 10:54:33 AM UTC 24 |
Oct 09 10:54:52 AM UTC 24 |
375626409 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.2680654006 |
|
|
Oct 09 10:54:04 AM UTC 24 |
Oct 09 10:54:29 AM UTC 24 |
845129219 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.1118474772 |
|
|
Oct 09 10:54:01 AM UTC 24 |
Oct 09 10:54:29 AM UTC 24 |
275600878 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.2062127907 |
|
|
Oct 09 10:54:27 AM UTC 24 |
Oct 09 10:54:29 AM UTC 24 |
39326375 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.1067938380 |
|
|
Oct 09 10:54:27 AM UTC 24 |
Oct 09 10:54:30 AM UTC 24 |
31554865 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3858074269 |
|
|
Oct 09 10:54:28 AM UTC 24 |
Oct 09 10:54:31 AM UTC 24 |
29357844 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.3996048150 |
|
|
Oct 09 10:54:07 AM UTC 24 |
Oct 09 10:54:32 AM UTC 24 |
705768891 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.465252396 |
|
|
Oct 09 10:54:21 AM UTC 24 |
Oct 09 10:54:53 AM UTC 24 |
287173823 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.4089204456 |
|
|
Oct 09 10:54:21 AM UTC 24 |
Oct 09 10:54:32 AM UTC 24 |
118689628 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.2928565579 |
|
|
Oct 09 10:54:16 AM UTC 24 |
Oct 09 10:54:33 AM UTC 24 |
368627449 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.2908410362 |
|
|
Oct 09 10:54:16 AM UTC 24 |
Oct 09 10:54:34 AM UTC 24 |
1515138318 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.539968171 |
|
|
Oct 09 10:53:50 AM UTC 24 |
Oct 09 10:54:34 AM UTC 24 |
8055442318 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.757993540 |
|
|
Oct 09 10:54:13 AM UTC 24 |
Oct 09 10:54:36 AM UTC 24 |
1481376798 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.2573121669 |
|
|
Oct 09 10:54:52 AM UTC 24 |
Oct 09 10:54:55 AM UTC 24 |
20935068 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.1627465301 |
|
|
Oct 09 10:54:25 AM UTC 24 |
Oct 09 10:54:36 AM UTC 24 |
184513088 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.702107138 |
|
|
Oct 09 10:54:33 AM UTC 24 |
Oct 09 10:54:52 AM UTC 24 |
6168427643 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.1095554062 |
|
|
Oct 09 10:54:30 AM UTC 24 |
Oct 09 10:54:37 AM UTC 24 |
165371605 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.242114973 |
|
|
Oct 09 10:54:24 AM UTC 24 |
Oct 09 10:54:37 AM UTC 24 |
485959852 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.911452651 |
|
|
Oct 09 10:54:22 AM UTC 24 |
Oct 09 10:54:37 AM UTC 24 |
699159697 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.598835119 |
|
|
Oct 09 10:54:36 AM UTC 24 |
Oct 09 10:54:39 AM UTC 24 |
53247790 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.155785777 |
|
|
Oct 09 10:54:24 AM UTC 24 |
Oct 09 10:54:39 AM UTC 24 |
328025387 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.3441805598 |
|
|
Oct 09 10:54:26 AM UTC 24 |
Oct 09 10:54:39 AM UTC 24 |
1315074909 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.1041689756 |
|
|
Oct 09 10:54:30 AM UTC 24 |
Oct 09 10:54:39 AM UTC 24 |
3093509864 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.2385210447 |
|
|
Oct 09 10:53:46 AM UTC 24 |
Oct 09 10:54:40 AM UTC 24 |
5384157300 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.1849542916 |
|
|
Oct 09 10:54:09 AM UTC 24 |
Oct 09 10:54:40 AM UTC 24 |
2350891287 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3211496349 |
|
|
Oct 09 10:54:38 AM UTC 24 |
Oct 09 10:54:40 AM UTC 24 |
127099119 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.1857542600 |
|
|
Oct 09 10:54:38 AM UTC 24 |
Oct 09 10:54:40 AM UTC 24 |
14546041 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.706979826 |
|
|
Oct 09 10:52:49 AM UTC 24 |
Oct 09 10:54:41 AM UTC 24 |
2799975692 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.2910107035 |
|
|
Oct 09 10:54:30 AM UTC 24 |
Oct 09 10:54:43 AM UTC 24 |
76563502 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.3594446461 |
|
|
Oct 09 10:54:40 AM UTC 24 |
Oct 09 10:54:44 AM UTC 24 |
36674761 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.2972759667 |
|
|
Oct 09 10:54:26 AM UTC 24 |
Oct 09 10:54:45 AM UTC 24 |
2045450915 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.3557965177 |
|
|
Oct 09 10:54:43 AM UTC 24 |
Oct 09 10:54:45 AM UTC 24 |
24828407 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.1144467370 |
|
|
Oct 09 10:54:24 AM UTC 24 |
Oct 09 10:54:46 AM UTC 24 |
3344908134 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4242119803 |
|
|
Oct 09 10:54:44 AM UTC 24 |
Oct 09 10:54:47 AM UTC 24 |
16440562 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.2263567717 |
|
|
Oct 09 10:54:43 AM UTC 24 |
Oct 09 10:54:47 AM UTC 24 |
146755126 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.3858943591 |
|
|
Oct 09 10:54:40 AM UTC 24 |
Oct 09 10:54:48 AM UTC 24 |
1253067113 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.530350225 |
|
|
Oct 09 10:54:30 AM UTC 24 |
Oct 09 10:54:49 AM UTC 24 |
940387987 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.1362741188 |
|
|
Oct 09 10:54:40 AM UTC 24 |
Oct 09 10:54:49 AM UTC 24 |
779847616 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.2003413492 |
|
|
Oct 09 10:54:30 AM UTC 24 |
Oct 09 10:54:49 AM UTC 24 |
1188650362 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.1552985236 |
|
|
Oct 09 10:54:40 AM UTC 24 |
Oct 09 10:54:49 AM UTC 24 |
113176386 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.3197403007 |
|
|
Oct 09 10:53:44 AM UTC 24 |
Oct 09 10:54:50 AM UTC 24 |
3484904176 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.3686494733 |
|
|
Oct 09 10:54:32 AM UTC 24 |
Oct 09 10:54:50 AM UTC 24 |
848517889 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.2727792968 |
|
|
Oct 09 10:54:48 AM UTC 24 |
Oct 09 10:54:52 AM UTC 24 |
193632218 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.2915391859 |
|
|
Oct 09 10:53:37 AM UTC 24 |
Oct 09 10:54:53 AM UTC 24 |
4702569470 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.2045371332 |
|
|
Oct 09 10:54:40 AM UTC 24 |
Oct 09 10:54:54 AM UTC 24 |
2679674918 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1419555050 |
|
|
Oct 09 10:55:39 AM UTC 24 |
Oct 09 10:55:41 AM UTC 24 |
25077327 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3672010633 |
|
|
Oct 09 10:54:52 AM UTC 24 |
Oct 09 10:54:54 AM UTC 24 |
12680145 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.2900637712 |
|
|
Oct 09 10:54:45 AM UTC 24 |
Oct 09 10:54:56 AM UTC 24 |
130658250 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.1727535220 |
|
|
Oct 09 10:54:52 AM UTC 24 |
Oct 09 10:54:57 AM UTC 24 |
152044090 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.1723849020 |
|
|
Oct 09 10:54:40 AM UTC 24 |
Oct 09 10:54:57 AM UTC 24 |
583640079 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.2651097559 |
|
|
Oct 09 10:54:42 AM UTC 24 |
Oct 09 10:54:57 AM UTC 24 |
2404773561 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2229603564 |
|
|
Oct 09 10:53:52 AM UTC 24 |
Oct 09 10:54:58 AM UTC 24 |
3154987506 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.309411340 |
|
|
Oct 09 10:54:54 AM UTC 24 |
Oct 09 10:55:00 AM UTC 24 |
190665837 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.225110419 |
|
|
Oct 09 10:53:32 AM UTC 24 |
Oct 09 10:55:00 AM UTC 24 |
14040178050 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.2283194434 |
|
|
Oct 09 10:54:57 AM UTC 24 |
Oct 09 10:55:00 AM UTC 24 |
18423046 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.759088623 |
|
|
Oct 09 10:54:59 AM UTC 24 |
Oct 09 10:55:01 AM UTC 24 |
32645614 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.4113542989 |
|
|
Oct 09 10:54:56 AM UTC 24 |
Oct 09 10:55:02 AM UTC 24 |
324591406 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.1411139188 |
|
|
Oct 09 10:54:38 AM UTC 24 |
Oct 09 10:55:02 AM UTC 24 |
399692912 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.1364984098 |
|
|
Oct 09 10:54:40 AM UTC 24 |
Oct 09 10:55:03 AM UTC 24 |
6245287593 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.4234965926 |
|
|
Oct 09 10:54:47 AM UTC 24 |
Oct 09 10:55:04 AM UTC 24 |
5867919835 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.1721761695 |
|
|
Oct 09 10:54:54 AM UTC 24 |
Oct 09 10:55:04 AM UTC 24 |
85232407 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.4157915125 |
|
|
Oct 09 10:54:28 AM UTC 24 |
Oct 09 10:55:04 AM UTC 24 |
243715001 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1142989819 |
|
|
Oct 09 10:53:20 AM UTC 24 |
Oct 09 10:55:04 AM UTC 24 |
3403574148 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.2482315975 |
|
|
Oct 09 10:54:59 AM UTC 24 |
Oct 09 10:55:05 AM UTC 24 |
575063580 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.1506144688 |
|
|
Oct 09 10:54:48 AM UTC 24 |
Oct 09 10:55:05 AM UTC 24 |
415070759 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.2157692871 |
|
|
Oct 09 10:54:56 AM UTC 24 |
Oct 09 10:55:06 AM UTC 24 |
268896299 ps |