| T177 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.2733151547 |
|
|
Oct 09 10:55:02 AM UTC 24 |
Oct 09 10:55:07 AM UTC 24 |
173045745 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2113904534 |
|
|
Oct 09 10:54:56 AM UTC 24 |
Oct 09 10:55:07 AM UTC 24 |
417308948 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.2464600854 |
|
|
Oct 09 10:54:50 AM UTC 24 |
Oct 09 10:55:08 AM UTC 24 |
2268504522 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.1730075143 |
|
|
Oct 09 10:55:39 AM UTC 24 |
Oct 09 10:55:41 AM UTC 24 |
18114663 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.2465526954 |
|
|
Oct 09 10:54:50 AM UTC 24 |
Oct 09 10:55:09 AM UTC 24 |
756709097 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.36874015 |
|
|
Oct 09 10:55:07 AM UTC 24 |
Oct 09 10:55:09 AM UTC 24 |
21688647 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3686517067 |
|
|
Oct 09 10:55:07 AM UTC 24 |
Oct 09 10:55:09 AM UTC 24 |
49087816 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.999239696 |
|
|
Oct 09 10:54:47 AM UTC 24 |
Oct 09 10:55:10 AM UTC 24 |
2008076771 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.575113126 |
|
|
Oct 09 10:54:56 AM UTC 24 |
Oct 09 10:55:10 AM UTC 24 |
223531042 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.2483697393 |
|
|
Oct 09 10:55:02 AM UTC 24 |
Oct 09 10:55:11 AM UTC 24 |
520816781 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.239480289 |
|
|
Oct 09 10:55:01 AM UTC 24 |
Oct 09 10:55:12 AM UTC 24 |
300407875 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.4011857476 |
|
|
Oct 09 10:55:07 AM UTC 24 |
Oct 09 10:55:12 AM UTC 24 |
178369657 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.1388263325 |
|
|
Oct 09 10:55:09 AM UTC 24 |
Oct 09 10:55:13 AM UTC 24 |
40799613 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.74286662 |
|
|
Oct 09 10:54:44 AM UTC 24 |
Oct 09 10:55:14 AM UTC 24 |
1384561161 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.2183771823 |
|
|
Oct 09 10:55:10 AM UTC 24 |
Oct 09 10:55:15 AM UTC 24 |
150790090 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.2212079928 |
|
|
Oct 09 10:55:04 AM UTC 24 |
Oct 09 10:55:16 AM UTC 24 |
792108130 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.1647531027 |
|
|
Oct 09 10:55:04 AM UTC 24 |
Oct 09 10:55:16 AM UTC 24 |
1286169762 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.3859718901 |
|
|
Oct 09 10:55:14 AM UTC 24 |
Oct 09 10:55:17 AM UTC 24 |
71203507 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2839072032 |
|
|
Oct 09 10:55:14 AM UTC 24 |
Oct 09 10:55:17 AM UTC 24 |
13392351 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.2414290166 |
|
|
Oct 09 10:55:02 AM UTC 24 |
Oct 09 10:55:17 AM UTC 24 |
807986332 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.2784126110 |
|
|
Oct 09 10:52:20 AM UTC 24 |
Oct 09 10:55:18 AM UTC 24 |
13943520855 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.3181768303 |
|
|
Oct 09 10:54:56 AM UTC 24 |
Oct 09 10:55:18 AM UTC 24 |
997932161 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.2095603157 |
|
|
Oct 09 10:55:14 AM UTC 24 |
Oct 09 10:55:18 AM UTC 24 |
41907636 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.1503711494 |
|
|
Oct 09 10:54:54 AM UTC 24 |
Oct 09 10:55:19 AM UTC 24 |
662122032 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.60887919 |
|
|
Oct 09 10:55:10 AM UTC 24 |
Oct 09 10:55:21 AM UTC 24 |
268517362 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.2858500747 |
|
|
Oct 09 10:55:17 AM UTC 24 |
Oct 09 10:55:21 AM UTC 24 |
309087402 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.1130995279 |
|
|
Oct 09 10:55:04 AM UTC 24 |
Oct 09 10:55:23 AM UTC 24 |
1314326292 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.1654273078 |
|
|
Oct 09 10:55:09 AM UTC 24 |
Oct 09 10:55:24 AM UTC 24 |
62775401 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.4205308508 |
|
|
Oct 09 10:54:52 AM UTC 24 |
Oct 09 10:55:25 AM UTC 24 |
286453403 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.14430702 |
|
|
Oct 09 10:55:22 AM UTC 24 |
Oct 09 10:55:25 AM UTC 24 |
19561599 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.2276996695 |
|
|
Oct 09 10:55:10 AM UTC 24 |
Oct 09 10:55:25 AM UTC 24 |
580219592 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.3487583563 |
|
|
Oct 09 10:55:12 AM UTC 24 |
Oct 09 10:55:25 AM UTC 24 |
885951308 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.3700355447 |
|
|
Oct 09 10:55:22 AM UTC 24 |
Oct 09 10:55:25 AM UTC 24 |
21338333 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.1967010247 |
|
|
Oct 09 10:55:10 AM UTC 24 |
Oct 09 10:55:26 AM UTC 24 |
614462825 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.181848982 |
|
|
Oct 09 10:55:24 AM UTC 24 |
Oct 09 10:55:27 AM UTC 24 |
110238232 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2604434360 |
|
|
Oct 09 10:55:19 AM UTC 24 |
Oct 09 10:55:28 AM UTC 24 |
1183895417 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.1064906677 |
|
|
Oct 09 10:55:16 AM UTC 24 |
Oct 09 10:55:29 AM UTC 24 |
146508118 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.2785316070 |
|
|
Oct 09 10:55:07 AM UTC 24 |
Oct 09 10:55:29 AM UTC 24 |
6854842266 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.1571750337 |
|
|
Oct 09 10:55:12 AM UTC 24 |
Oct 09 10:55:30 AM UTC 24 |
1539943603 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.4137666044 |
|
|
Oct 09 10:55:27 AM UTC 24 |
Oct 09 10:55:32 AM UTC 24 |
80077105 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.2463382525 |
|
|
Oct 09 10:55:27 AM UTC 24 |
Oct 09 10:55:39 AM UTC 24 |
1943570586 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.2713125452 |
|
|
Oct 09 10:55:16 AM UTC 24 |
Oct 09 10:55:41 AM UTC 24 |
429338482 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.3815499308 |
|
|
Oct 09 10:55:17 AM UTC 24 |
Oct 09 10:55:33 AM UTC 24 |
359505645 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.607538242 |
|
|
Oct 09 10:55:27 AM UTC 24 |
Oct 09 10:55:34 AM UTC 24 |
1218408348 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.2779425518 |
|
|
Oct 09 10:55:31 AM UTC 24 |
Oct 09 10:55:34 AM UTC 24 |
185482796 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.2935916679 |
|
|
Oct 09 10:55:19 AM UTC 24 |
Oct 09 10:55:34 AM UTC 24 |
281115510 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.2805475462 |
|
|
Oct 09 10:55:19 AM UTC 24 |
Oct 09 10:55:34 AM UTC 24 |
1316890816 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.585914771 |
|
|
Oct 09 10:55:19 AM UTC 24 |
Oct 09 10:55:34 AM UTC 24 |
403925307 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3969806918 |
|
|
Oct 09 10:55:19 AM UTC 24 |
Oct 09 10:55:35 AM UTC 24 |
299565656 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.345002977 |
|
|
Oct 09 10:55:34 AM UTC 24 |
Oct 09 10:55:36 AM UTC 24 |
20396335 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.2064122021 |
|
|
Oct 09 10:55:07 AM UTC 24 |
Oct 09 10:55:36 AM UTC 24 |
225753121 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.2546802683 |
|
|
Oct 09 10:55:33 AM UTC 24 |
Oct 09 10:55:37 AM UTC 24 |
110020961 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.2243613094 |
|
|
Oct 09 10:55:01 AM UTC 24 |
Oct 09 10:55:37 AM UTC 24 |
3120732605 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.2353475244 |
|
|
Oct 09 10:55:26 AM UTC 24 |
Oct 09 10:55:37 AM UTC 24 |
180360402 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.1801799887 |
|
|
Oct 09 10:55:28 AM UTC 24 |
Oct 09 10:55:37 AM UTC 24 |
1086487743 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.3364883093 |
|
|
Oct 09 10:55:36 AM UTC 24 |
Oct 09 10:55:39 AM UTC 24 |
82894821 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3039906859 |
|
|
Oct 09 10:55:27 AM UTC 24 |
Oct 09 10:55:40 AM UTC 24 |
234798647 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.1280539077 |
|
|
Oct 09 10:55:30 AM UTC 24 |
Oct 09 10:55:42 AM UTC 24 |
700799030 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.4282580956 |
|
|
Oct 09 10:55:39 AM UTC 24 |
Oct 09 10:55:44 AM UTC 24 |
320389460 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.1649892446 |
|
|
Oct 09 10:56:23 AM UTC 24 |
Oct 09 10:56:36 AM UTC 24 |
474260806 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.3186137853 |
|
|
Oct 09 10:58:12 AM UTC 24 |
Oct 09 10:58:41 AM UTC 24 |
219702225 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.4198491869 |
|
|
Oct 09 10:55:28 AM UTC 24 |
Oct 09 10:55:44 AM UTC 24 |
905979929 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.1175472972 |
|
|
Oct 09 10:55:42 AM UTC 24 |
Oct 09 10:55:45 AM UTC 24 |
32143796 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.479519966 |
|
|
Oct 09 10:55:41 AM UTC 24 |
Oct 09 10:55:46 AM UTC 24 |
1052770749 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.1252404909 |
|
|
Oct 09 10:55:36 AM UTC 24 |
Oct 09 10:55:46 AM UTC 24 |
221467652 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.3843271304 |
|
|
Oct 09 10:55:36 AM UTC 24 |
Oct 09 10:55:47 AM UTC 24 |
412488774 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.3554380064 |
|
|
Oct 09 10:55:36 AM UTC 24 |
Oct 09 10:55:48 AM UTC 24 |
3275573204 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.1323970262 |
|
|
Oct 09 10:55:40 AM UTC 24 |
Oct 09 10:55:48 AM UTC 24 |
42234667 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.1386610489 |
|
|
Oct 09 10:55:46 AM UTC 24 |
Oct 09 10:55:49 AM UTC 24 |
21956684 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2315063740 |
|
|
Oct 09 10:55:48 AM UTC 24 |
Oct 09 10:55:50 AM UTC 24 |
92378366 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.1367060838 |
|
|
Oct 09 10:55:38 AM UTC 24 |
Oct 09 10:55:51 AM UTC 24 |
230209217 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.86675413 |
|
|
Oct 09 10:55:36 AM UTC 24 |
Oct 09 10:55:52 AM UTC 24 |
1314033892 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3196612044 |
|
|
Oct 09 10:55:36 AM UTC 24 |
Oct 09 10:55:52 AM UTC 24 |
581945109 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.4273179807 |
|
|
Oct 09 10:54:07 AM UTC 24 |
Oct 09 10:55:53 AM UTC 24 |
12250641745 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.1783813232 |
|
|
Oct 09 10:55:24 AM UTC 24 |
Oct 09 10:55:53 AM UTC 24 |
1116765693 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.2746053488 |
|
|
Oct 09 10:55:50 AM UTC 24 |
Oct 09 10:55:54 AM UTC 24 |
88977700 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.1176416113 |
|
|
Oct 09 10:54:50 AM UTC 24 |
Oct 09 10:56:37 AM UTC 24 |
2627335659 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.473396372 |
|
|
Oct 09 10:55:48 AM UTC 24 |
Oct 09 10:55:54 AM UTC 24 |
48914648 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.3776191563 |
|
|
Oct 09 10:55:42 AM UTC 24 |
Oct 09 10:55:56 AM UTC 24 |
311350537 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.3695242129 |
|
|
Oct 09 10:55:41 AM UTC 24 |
Oct 09 10:55:57 AM UTC 24 |
2633307050 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.1185604995 |
|
|
Oct 09 10:58:16 AM UTC 24 |
Oct 09 10:58:42 AM UTC 24 |
414780276 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.3018892187 |
|
|
Oct 09 10:55:44 AM UTC 24 |
Oct 09 10:55:58 AM UTC 24 |
307673834 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.2476549536 |
|
|
Oct 09 10:55:56 AM UTC 24 |
Oct 09 10:55:59 AM UTC 24 |
64280535 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1388024129 |
|
|
Oct 09 10:55:58 AM UTC 24 |
Oct 09 10:56:00 AM UTC 24 |
14935949 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.3362361132 |
|
|
Oct 09 10:55:50 AM UTC 24 |
Oct 09 10:56:01 AM UTC 24 |
55541957 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1215472000 |
|
|
Oct 09 10:55:42 AM UTC 24 |
Oct 09 10:56:02 AM UTC 24 |
1757535862 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.2968714363 |
|
|
Oct 09 10:55:58 AM UTC 24 |
Oct 09 10:56:02 AM UTC 24 |
105701155 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.3739339113 |
|
|
Oct 09 10:55:52 AM UTC 24 |
Oct 09 10:56:03 AM UTC 24 |
211480748 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.1317616563 |
|
|
Oct 09 10:55:45 AM UTC 24 |
Oct 09 10:56:03 AM UTC 24 |
3032225984 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.324188926 |
|
|
Oct 09 10:55:39 AM UTC 24 |
Oct 09 10:56:04 AM UTC 24 |
261676190 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.504718500 |
|
|
Oct 09 10:55:54 AM UTC 24 |
Oct 09 10:56:05 AM UTC 24 |
486736044 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2926284286 |
|
|
Oct 09 10:56:31 AM UTC 24 |
Oct 09 10:56:38 AM UTC 24 |
465076359 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.2790450656 |
|
|
Oct 09 10:55:56 AM UTC 24 |
Oct 09 10:56:07 AM UTC 24 |
1724612787 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.3713557364 |
|
|
Oct 09 10:56:02 AM UTC 24 |
Oct 09 10:56:07 AM UTC 24 |
55970614 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.439286399 |
|
|
Oct 09 10:55:52 AM UTC 24 |
Oct 09 10:56:08 AM UTC 24 |
630620221 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.4291133433 |
|
|
Oct 09 10:56:31 AM UTC 24 |
Oct 09 10:56:34 AM UTC 24 |
17946368 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.277779746 |
|
|
Oct 09 10:56:22 AM UTC 24 |
Oct 09 10:56:36 AM UTC 24 |
967603195 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.1556199762 |
|
|
Oct 09 10:55:36 AM UTC 24 |
Oct 09 10:56:09 AM UTC 24 |
1927438166 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.3363216566 |
|
|
Oct 09 10:55:59 AM UTC 24 |
Oct 09 10:56:09 AM UTC 24 |
1213558354 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.2077001113 |
|
|
Oct 09 10:55:56 AM UTC 24 |
Oct 09 10:56:09 AM UTC 24 |
324865907 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.2347304784 |
|
|
Oct 09 10:56:08 AM UTC 24 |
Oct 09 10:56:11 AM UTC 24 |
40665501 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3092293476 |
|
|
Oct 09 10:55:54 AM UTC 24 |
Oct 09 10:56:11 AM UTC 24 |
4984114002 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.2244601531 |
|
|
Oct 09 10:56:08 AM UTC 24 |
Oct 09 10:56:13 AM UTC 24 |
38471851 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3262480625 |
|
|
Oct 09 10:56:10 AM UTC 24 |
Oct 09 10:56:13 AM UTC 24 |
17864988 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.2810209856 |
|
|
Oct 09 10:56:11 AM UTC 24 |
Oct 09 10:56:14 AM UTC 24 |
87971359 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2406146878 |
|
|
Oct 09 10:56:03 AM UTC 24 |
Oct 09 10:56:15 AM UTC 24 |
674140701 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.311337688 |
|
|
Oct 09 10:55:36 AM UTC 24 |
Oct 09 10:56:16 AM UTC 24 |
330390997 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.3367451793 |
|
|
Oct 09 10:56:36 AM UTC 24 |
Oct 09 10:56:39 AM UTC 24 |
145865877 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.1466119056 |
|
|
Oct 09 10:56:03 AM UTC 24 |
Oct 09 10:56:17 AM UTC 24 |
219907735 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.4088132315 |
|
|
Oct 09 10:56:05 AM UTC 24 |
Oct 09 10:56:18 AM UTC 24 |
355167474 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.4165474974 |
|
|
Oct 09 10:56:06 AM UTC 24 |
Oct 09 10:56:18 AM UTC 24 |
396726173 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.2670099880 |
|
|
Oct 09 10:56:03 AM UTC 24 |
Oct 09 10:56:19 AM UTC 24 |
1069789304 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2793024794 |
|
|
Oct 09 10:56:17 AM UTC 24 |
Oct 09 10:56:19 AM UTC 24 |
96870949 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.8256000 |
|
|
Oct 09 10:54:18 AM UTC 24 |
Oct 09 10:56:20 AM UTC 24 |
6410913274 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3751358160 |
|
|
Oct 09 10:54:42 AM UTC 24 |
Oct 09 10:56:20 AM UTC 24 |
10260490195 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.939063673 |
|
|
Oct 09 10:56:11 AM UTC 24 |
Oct 09 10:56:21 AM UTC 24 |
217354031 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.278834542 |
|
|
Oct 09 10:56:18 AM UTC 24 |
Oct 09 10:56:21 AM UTC 24 |
125751823 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.2429282037 |
|
|
Oct 09 10:56:11 AM UTC 24 |
Oct 09 10:56:21 AM UTC 24 |
733860295 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.4009085622 |
|
|
Oct 09 10:56:19 AM UTC 24 |
Oct 09 10:56:22 AM UTC 24 |
69840838 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.1912194324 |
|
|
Oct 09 10:56:12 AM UTC 24 |
Oct 09 10:56:22 AM UTC 24 |
507171203 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.1632257558 |
|
|
Oct 09 10:56:02 AM UTC 24 |
Oct 09 10:56:23 AM UTC 24 |
351337330 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3388256000 |
|
|
Oct 09 10:56:11 AM UTC 24 |
Oct 09 10:56:24 AM UTC 24 |
2973315378 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.1567423454 |
|
|
Oct 09 10:56:14 AM UTC 24 |
Oct 09 10:56:25 AM UTC 24 |
1197201091 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.3498962534 |
|
|
Oct 09 10:56:22 AM UTC 24 |
Oct 09 10:56:26 AM UTC 24 |
201142489 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.2385000246 |
|
|
Oct 09 10:56:25 AM UTC 24 |
Oct 09 10:56:28 AM UTC 24 |
139853373 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.2511317500 |
|
|
Oct 09 10:56:22 AM UTC 24 |
Oct 09 10:56:28 AM UTC 24 |
219744685 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.865844217 |
|
|
Oct 09 10:55:59 AM UTC 24 |
Oct 09 10:56:29 AM UTC 24 |
1583930117 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.355438923 |
|
|
Oct 09 10:55:49 AM UTC 24 |
Oct 09 10:56:29 AM UTC 24 |
1413459142 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2197046434 |
|
|
Oct 09 10:56:28 AM UTC 24 |
Oct 09 10:56:30 AM UTC 24 |
30592225 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1973957541 |
|
|
Oct 09 10:56:12 AM UTC 24 |
Oct 09 10:56:30 AM UTC 24 |
420037035 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.701316285 |
|
|
Oct 09 10:56:27 AM UTC 24 |
Oct 09 10:56:30 AM UTC 24 |
28812884 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.3674167377 |
|
|
Oct 09 10:56:36 AM UTC 24 |
Oct 09 10:56:38 AM UTC 24 |
92209466 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.422346884 |
|
|
Oct 09 10:56:11 AM UTC 24 |
Oct 09 10:56:32 AM UTC 24 |
1893267162 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1899674535 |
|
|
Oct 09 10:56:22 AM UTC 24 |
Oct 09 10:56:34 AM UTC 24 |
682506976 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.1050197143 |
|
|
Oct 09 10:56:24 AM UTC 24 |
Oct 09 10:56:35 AM UTC 24 |
1109707006 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.2614818638 |
|
|
Oct 09 10:56:29 AM UTC 24 |
Oct 09 10:56:36 AM UTC 24 |
224896342 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.101140125 |
|
|
Oct 09 10:56:37 AM UTC 24 |
Oct 09 10:56:40 AM UTC 24 |
10922986 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.2956872307 |
|
|
Oct 09 10:58:22 AM UTC 24 |
Oct 09 10:58:39 AM UTC 24 |
1224743728 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.2042680637 |
|
|
Oct 09 10:55:38 AM UTC 24 |
Oct 09 10:56:41 AM UTC 24 |
1678059096 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3235127777 |
|
|
Oct 09 10:56:15 AM UTC 24 |
Oct 09 10:56:42 AM UTC 24 |
3537064243 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.2171647403 |
|
|
Oct 09 10:56:19 AM UTC 24 |
Oct 09 10:56:42 AM UTC 24 |
2862186645 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.3387765024 |
|
|
Oct 09 10:56:33 AM UTC 24 |
Oct 09 10:56:43 AM UTC 24 |
3556215269 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.4249398915 |
|
|
Oct 09 10:56:39 AM UTC 24 |
Oct 09 10:56:43 AM UTC 24 |
29398081 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.3607582285 |
|
|
Oct 09 10:52:33 AM UTC 24 |
Oct 09 10:56:44 AM UTC 24 |
19510146659 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.1750598490 |
|
|
Oct 09 10:56:31 AM UTC 24 |
Oct 09 10:56:44 AM UTC 24 |
202445408 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.2515913645 |
|
|
Oct 09 10:56:22 AM UTC 24 |
Oct 09 10:56:44 AM UTC 24 |
1402728748 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.2076905624 |
|
|
Oct 09 10:56:37 AM UTC 24 |
Oct 09 10:56:45 AM UTC 24 |
150226947 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.641759172 |
|
|
Oct 09 10:56:22 AM UTC 24 |
Oct 09 10:56:46 AM UTC 24 |
4088042760 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.282748805 |
|
|
Oct 09 10:56:44 AM UTC 24 |
Oct 09 10:56:47 AM UTC 24 |
20276376 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.3520815452 |
|
|
Oct 09 10:56:31 AM UTC 24 |
Oct 09 10:56:47 AM UTC 24 |
2478156026 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3177682305 |
|
|
Oct 09 10:56:46 AM UTC 24 |
Oct 09 10:56:49 AM UTC 24 |
15073722 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.4054023484 |
|
|
Oct 09 10:56:29 AM UTC 24 |
Oct 09 10:56:50 AM UTC 24 |
177555349 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.2192334987 |
|
|
Oct 09 10:56:46 AM UTC 24 |
Oct 09 10:56:50 AM UTC 24 |
310068830 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1346582430 |
|
|
Oct 09 10:56:31 AM UTC 24 |
Oct 09 10:56:51 AM UTC 24 |
3534275712 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1984731435 |
|
|
Oct 09 10:55:30 AM UTC 24 |
Oct 09 10:56:54 AM UTC 24 |
4034176485 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.1359501273 |
|
|
Oct 09 10:56:48 AM UTC 24 |
Oct 09 10:56:55 AM UTC 24 |
65585838 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.2045543742 |
|
|
Oct 09 10:56:39 AM UTC 24 |
Oct 09 10:56:57 AM UTC 24 |
344788875 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.4169607293 |
|
|
Oct 09 10:56:42 AM UTC 24 |
Oct 09 10:56:58 AM UTC 24 |
960893811 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.195199268 |
|
|
Oct 09 10:56:44 AM UTC 24 |
Oct 09 10:56:58 AM UTC 24 |
775640158 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.3939199853 |
|
|
Oct 09 10:56:46 AM UTC 24 |
Oct 09 10:56:58 AM UTC 24 |
227452209 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.1585473942 |
|
|
Oct 09 10:56:33 AM UTC 24 |
Oct 09 10:56:59 AM UTC 24 |
956726805 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.3696181387 |
|
|
Oct 09 10:56:57 AM UTC 24 |
Oct 09 10:57:00 AM UTC 24 |
41486218 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.3015996924 |
|
|
Oct 09 10:56:41 AM UTC 24 |
Oct 09 10:57:01 AM UTC 24 |
2862104057 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1047687920 |
|
|
Oct 09 10:56:41 AM UTC 24 |
Oct 09 10:57:02 AM UTC 24 |
334014194 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.1340073982 |
|
|
Oct 09 10:56:48 AM UTC 24 |
Oct 09 10:57:02 AM UTC 24 |
577671969 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.3360582337 |
|
|
Oct 09 10:56:39 AM UTC 24 |
Oct 09 10:57:02 AM UTC 24 |
751439072 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.264440867 |
|
|
Oct 09 10:56:48 AM UTC 24 |
Oct 09 10:57:02 AM UTC 24 |
1009918256 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.2587494640 |
|
|
Oct 09 10:56:44 AM UTC 24 |
Oct 09 10:57:39 AM UTC 24 |
1567413358 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.922745355 |
|
|
Oct 09 10:57:00 AM UTC 24 |
Oct 09 10:57:03 AM UTC 24 |
34171685 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.988348612 |
|
|
Oct 09 10:56:50 AM UTC 24 |
Oct 09 10:57:03 AM UTC 24 |
616050188 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.2955651688 |
|
|
Oct 09 10:57:00 AM UTC 24 |
Oct 09 10:57:04 AM UTC 24 |
46812085 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.2418415136 |
|
|
Oct 09 10:53:58 AM UTC 24 |
Oct 09 10:57:04 AM UTC 24 |
11343207602 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.2223078848 |
|
|
Oct 09 10:56:51 AM UTC 24 |
Oct 09 10:57:06 AM UTC 24 |
1208757747 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.1473451513 |
|
|
Oct 09 10:57:02 AM UTC 24 |
Oct 09 10:57:07 AM UTC 24 |
137182458 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.390588363 |
|
|
Oct 09 10:56:51 AM UTC 24 |
Oct 09 10:57:08 AM UTC 24 |
401268591 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.1982652179 |
|
|
Oct 09 10:57:06 AM UTC 24 |
Oct 09 10:57:08 AM UTC 24 |
37773663 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.2983992958 |
|
|
Oct 09 10:57:05 AM UTC 24 |
Oct 09 10:57:09 AM UTC 24 |
207041712 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.219136924 |
|
|
Oct 09 10:55:07 AM UTC 24 |
Oct 09 10:57:11 AM UTC 24 |
11535241956 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1764398731 |
|
|
Oct 09 10:57:08 AM UTC 24 |
Oct 09 10:57:12 AM UTC 24 |
14528165 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.1232526761 |
|
|
Oct 09 10:57:08 AM UTC 24 |
Oct 09 10:57:12 AM UTC 24 |
56920552 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.2296338330 |
|
|
Oct 09 10:57:01 AM UTC 24 |
Oct 09 10:57:12 AM UTC 24 |
71903381 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2534798670 |
|
|
Oct 09 10:55:21 AM UTC 24 |
Oct 09 10:57:13 AM UTC 24 |
2856211462 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.133508901 |
|
|
Oct 09 10:57:10 AM UTC 24 |
Oct 09 10:57:14 AM UTC 24 |
21429703 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.4261320769 |
|
|
Oct 09 10:56:46 AM UTC 24 |
Oct 09 10:57:15 AM UTC 24 |
225881164 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.745422618 |
|
|
Oct 09 10:56:52 AM UTC 24 |
Oct 09 10:57:16 AM UTC 24 |
6157251482 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.2071899012 |
|
|
Oct 09 10:56:37 AM UTC 24 |
Oct 09 10:57:16 AM UTC 24 |
358419175 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.1488076960 |
|
|
Oct 09 10:57:02 AM UTC 24 |
Oct 09 10:57:17 AM UTC 24 |
301910492 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.3888032297 |
|
|
Oct 09 10:57:05 AM UTC 24 |
Oct 09 10:57:19 AM UTC 24 |
405742874 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.753333066 |
|
|
Oct 09 10:57:17 AM UTC 24 |
Oct 09 10:57:20 AM UTC 24 |
48574155 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.570041471 |
|
|
Oct 09 10:57:05 AM UTC 24 |
Oct 09 10:57:20 AM UTC 24 |
433896696 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.4164074011 |
|
|
Oct 09 10:57:19 AM UTC 24 |
Oct 09 10:57:22 AM UTC 24 |
88475575 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1829720074 |
|
|
Oct 09 10:57:18 AM UTC 24 |
Oct 09 10:57:22 AM UTC 24 |
26633223 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.3663888570 |
|
|
Oct 09 10:57:05 AM UTC 24 |
Oct 09 10:57:24 AM UTC 24 |
2400565662 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1212640918 |
|
|
Oct 09 10:57:11 AM UTC 24 |
Oct 09 10:57:24 AM UTC 24 |
1105361276 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.3454891396 |
|
|
Oct 09 10:57:10 AM UTC 24 |
Oct 09 10:57:27 AM UTC 24 |
204818808 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.2023060997 |
|
|
Oct 09 10:57:22 AM UTC 24 |
Oct 09 10:57:28 AM UTC 24 |
145591739 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.4146765889 |
|
|
Oct 09 10:57:22 AM UTC 24 |
Oct 09 10:57:28 AM UTC 24 |
219037289 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.2336240992 |
|
|
Oct 09 10:57:13 AM UTC 24 |
Oct 09 10:57:29 AM UTC 24 |
2237773746 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.2396050769 |
|
|
Oct 09 10:57:01 AM UTC 24 |
Oct 09 10:57:29 AM UTC 24 |
1111383391 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.1728400550 |
|
|
Oct 09 10:57:06 AM UTC 24 |
Oct 09 10:57:30 AM UTC 24 |
6285277337 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.4184223953 |
|
|
Oct 09 10:57:13 AM UTC 24 |
Oct 09 10:57:30 AM UTC 24 |
266097742 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.854614121 |
|
|
Oct 09 10:56:55 AM UTC 24 |
Oct 09 10:57:31 AM UTC 24 |
748185882 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.4288931830 |
|
|
Oct 09 10:57:13 AM UTC 24 |
Oct 09 10:57:32 AM UTC 24 |
1552656662 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3267711582 |
|
|
Oct 09 10:56:36 AM UTC 24 |
Oct 09 10:57:32 AM UTC 24 |
919333508 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.1175624884 |
|
|
Oct 09 10:57:15 AM UTC 24 |
Oct 09 10:57:33 AM UTC 24 |
533268266 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.799016260 |
|
|
Oct 09 10:57:30 AM UTC 24 |
Oct 09 10:57:33 AM UTC 24 |
13467548 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.2295304677 |
|
|
Oct 09 10:57:23 AM UTC 24 |
Oct 09 10:57:40 AM UTC 24 |
2507544973 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.871595622 |
|
|
Oct 09 10:57:13 AM UTC 24 |
Oct 09 10:57:35 AM UTC 24 |
2095306678 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1644164888 |
|
|
Oct 09 10:57:32 AM UTC 24 |
Oct 09 10:57:35 AM UTC 24 |
43521507 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.1469286283 |
|
|
Oct 09 10:57:08 AM UTC 24 |
Oct 09 10:57:35 AM UTC 24 |
895575164 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.3997134484 |
|
|
Oct 09 10:57:32 AM UTC 24 |
Oct 09 10:57:35 AM UTC 24 |
39006269 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.1011060060 |
|
|
Oct 09 10:57:26 AM UTC 24 |
Oct 09 10:57:38 AM UTC 24 |
1180627466 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.3181139796 |
|
|
Oct 09 10:57:34 AM UTC 24 |
Oct 09 10:57:38 AM UTC 24 |
133618211 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2180490737 |
|
|
Oct 09 10:55:56 AM UTC 24 |
Oct 09 10:57:39 AM UTC 24 |
2395637694 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.3008587755 |
|
|
Oct 09 10:57:29 AM UTC 24 |
Oct 09 10:57:39 AM UTC 24 |
473775221 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.742809602 |
|
|
Oct 09 10:57:34 AM UTC 24 |
Oct 09 10:57:41 AM UTC 24 |
1229542128 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.206011210 |
|
|
Oct 09 10:57:40 AM UTC 24 |
Oct 09 10:57:43 AM UTC 24 |
11236494 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.2314100775 |
|
|
Oct 09 10:57:40 AM UTC 24 |
Oct 09 10:57:43 AM UTC 24 |
61691282 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.790270879 |
|
|
Oct 09 10:57:34 AM UTC 24 |
Oct 09 10:57:45 AM UTC 24 |
1488043575 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.4124219117 |
|
|
Oct 09 10:57:23 AM UTC 24 |
Oct 09 10:57:46 AM UTC 24 |
3316676024 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.1409064622 |
|
|
Oct 09 10:57:40 AM UTC 24 |
Oct 09 10:57:46 AM UTC 24 |
315454830 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.2416323408 |
|
|
Oct 09 10:57:42 AM UTC 24 |
Oct 09 10:57:47 AM UTC 24 |
80566970 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.384043542 |
|
|
Oct 09 10:57:34 AM UTC 24 |
Oct 09 10:57:47 AM UTC 24 |
449966290 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.2397624456 |
|
|
Oct 09 10:57:36 AM UTC 24 |
Oct 09 10:57:49 AM UTC 24 |
195912421 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.2731847066 |
|
|
Oct 09 10:54:56 AM UTC 24 |
Oct 09 10:57:50 AM UTC 24 |
10779975797 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2543245544 |
|
|
Oct 09 10:57:36 AM UTC 24 |
Oct 09 10:57:50 AM UTC 24 |
1465288315 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.998034508 |
|
|
Oct 09 10:57:42 AM UTC 24 |
Oct 09 10:57:50 AM UTC 24 |
286936838 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.949850749 |
|
|
Oct 09 10:57:26 AM UTC 24 |
Oct 09 10:57:51 AM UTC 24 |
559744589 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.3273401600 |
|
|
Oct 09 10:57:36 AM UTC 24 |
Oct 09 10:57:52 AM UTC 24 |
289201992 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.1365057116 |
|
|
Oct 09 10:57:24 AM UTC 24 |
Oct 09 10:57:54 AM UTC 24 |
10194092565 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2765799403 |
|
|
Oct 09 10:57:52 AM UTC 24 |
Oct 09 10:57:54 AM UTC 24 |
28796188 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3345124062 |
|
|
Oct 09 10:57:52 AM UTC 24 |
Oct 09 10:57:55 AM UTC 24 |
12450499 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.1183126546 |
|
|
Oct 09 10:58:16 AM UTC 24 |
Oct 09 10:58:31 AM UTC 24 |
376301453 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.2917217282 |
|
|
Oct 09 10:57:52 AM UTC 24 |
Oct 09 10:57:56 AM UTC 24 |
171296013 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.1265683550 |
|
|
Oct 09 10:57:34 AM UTC 24 |
Oct 09 10:57:56 AM UTC 24 |
1289038841 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.1756126033 |
|
|
Oct 09 10:57:44 AM UTC 24 |
Oct 09 10:57:56 AM UTC 24 |
5187810516 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.707347267 |
|
|
Oct 09 10:57:20 AM UTC 24 |
Oct 09 10:57:59 AM UTC 24 |
242346775 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.966412722 |
|
|
Oct 09 10:57:44 AM UTC 24 |
Oct 09 10:57:59 AM UTC 24 |
290845972 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2232345078 |
|
|
Oct 09 10:57:06 AM UTC 24 |
Oct 09 10:57:59 AM UTC 24 |
1644494899 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1055679664 |
|
|
Oct 09 10:55:39 AM UTC 24 |
Oct 09 10:57:59 AM UTC 24 |
5280137119 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.3485776613 |
|
|
Oct 09 10:57:42 AM UTC 24 |
Oct 09 10:57:59 AM UTC 24 |
376839138 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.147351662 |
|
|
Oct 09 10:57:55 AM UTC 24 |
Oct 09 10:58:01 AM UTC 24 |
227587071 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.538950195 |
|
|
Oct 09 10:57:49 AM UTC 24 |
Oct 09 10:58:01 AM UTC 24 |
324941211 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2339044581 |
|
|
Oct 09 10:51:51 AM UTC 24 |
Oct 09 10:58:01 AM UTC 24 |
47970062719 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.3667027 |
|
|
Oct 09 10:55:12 AM UTC 24 |
Oct 09 10:58:02 AM UTC 24 |
6313598404 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.2445993447 |
|
|
Oct 09 10:57:32 AM UTC 24 |
Oct 09 10:58:03 AM UTC 24 |
406922980 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2481249170 |
|
|
Oct 09 10:58:02 AM UTC 24 |
Oct 09 10:58:04 AM UTC 24 |
25242953 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.4021793537 |
|
|
Oct 09 10:57:52 AM UTC 24 |
Oct 09 10:58:04 AM UTC 24 |
283700192 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.2948325018 |
|
|
Oct 09 10:58:02 AM UTC 24 |
Oct 09 10:58:04 AM UTC 24 |
71979288 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.3288357995 |
|
|
Oct 09 10:57:58 AM UTC 24 |
Oct 09 10:58:06 AM UTC 24 |
650573694 ps |