Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	777382	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

968082

1

T1

6

T2

19

T3

208

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1454028	1			T1	76		T2	31		T3	239
values[0x0]	145669	1			T1	4		T2	4		T3	65
values[0x1]	145767	1			T1	4		T2	4		T3	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	614891	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1130573

1

T1

32

T2

26

T3

234

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6246	1			T15	3		T16	10		T20	4
valid_sources[0x01]	5219	1			T4	5		T16	8		T20	2
valid_sources[0x02]	5230	1			T15	3		T16	9		T20	7
valid_sources[0x03]	5142	1			T16	12		T20	2		T21	7
valid_sources[0x04]	5596	1			T12	1		T4	2		T15	1
valid_sources[0x05]	5609	1			T4	1		T15	2		T16	8
valid_sources[0x06]	5128	1			T12	1		T15	1		T16	3
valid_sources[0x07]	5202	1			T12	1		T4	2		T15	11
valid_sources[0x08]	5005	1			T4	4		T16	12		T20	7
valid_sources[0x09]	5137	1			T15	3		T16	10		T20	2
valid_sources[0x0a]	6328	1			T15	9		T16	5		T21	5
valid_sources[0x0b]	5211	1			T4	2		T16	7		T20	7
valid_sources[0x0c]	6556	1			T4	1		T15	1		T16	4
valid_sources[0x0d]	6522	1			T16	8		T20	4		T30	2
valid_sources[0x0e]	15530	1			T4	1		T15	15		T16	9
valid_sources[0x0f]	5156	1			T4	2		T15	3		T16	5
valid_sources[0x10]	5633	1			T15	4		T16	8		T5	5
valid_sources[0x11]	7275	1			T4	1		T15	6		T16	8
valid_sources[0x12]	5157	1			T4	2		T15	1		T16	6
valid_sources[0x13]	5711	1			T16	3		T20	2		T21	11
valid_sources[0x14]	5327	1			T15	8		T16	9		T20	6
valid_sources[0x15]	5162	1			T4	2		T15	1		T16	9
valid_sources[0x16]	5171	1			T16	11		T20	2		T21	10
valid_sources[0x17]	7650	1			T12	1		T4	2		T16	13
valid_sources[0x18]	6386	1			T16	13		T20	1		T21	2
valid_sources[0x19]	5402	1			T4	2		T15	1		T16	6
valid_sources[0x1a]	5254	1			T12	1		T4	1		T16	11
valid_sources[0x1b]	5494	1			T15	2		T16	4		T20	3
valid_sources[0x1c]	5539	1			T4	1		T15	6		T16	11
valid_sources[0x1d]	5405	1			T16	16		T21	5		T22	2
valid_sources[0x1e]	9595	1			T4	1		T16	7		T20	1
valid_sources[0x1f]	6870	1			T3	353		T4	3		T15	1
valid_sources[0x20]	4966	1			T15	1		T16	3		T20	7
valid_sources[0x21]	6724	1			T4	1		T15	4		T16	13
valid_sources[0x22]	5449	1			T15	4		T16	6		T20	1
valid_sources[0x23]	7937	1			T4	1		T15	1		T16	12
valid_sources[0x24]	5221	1			T4	1		T15	3		T16	11
valid_sources[0x25]	5650	1			T15	1		T16	4		T20	5
valid_sources[0x26]	5282	1			T14	6		T16	8		T20	6
valid_sources[0x27]	37704	1			T15	2		T16	11		T20	1
valid_sources[0x28]	5959	1			T15	3		T16	10		T20	3
valid_sources[0x29]	5465	1			T16	4		T20	5		T21	1
valid_sources[0x2a]	17663	1			T15	1		T16	6		T20	1
valid_sources[0x2b]	8070	1			T15	4		T16	7		T20	4
valid_sources[0x2c]	5456	1			T4	1		T16	9		T5	1
valid_sources[0x2d]	5383	1			T4	2		T15	1		T16	7
valid_sources[0x2e]	6599	1			T4	1		T16	7		T20	1
valid_sources[0x2f]	6552	1			T4	3		T16	8		T20	1
valid_sources[0x30]	6987	1			T15	3		T16	9		T20	2
valid_sources[0x31]	5252	1			T4	1		T15	2		T16	3
valid_sources[0x32]	7405	1			T15	1		T16	5		T20	3
valid_sources[0x33]	5072	1			T4	2		T15	4		T16	4
valid_sources[0x34]	5798	1			T16	8		T20	2		T21	7
valid_sources[0x35]	5675	1			T12	1		T15	1		T16	6
valid_sources[0x36]	7344	1			T4	2		T16	3		T5	9
valid_sources[0x37]	6752	1			T16	9		T5	1		T20	7
valid_sources[0x38]	5346	1			T15	1		T16	9		T20	3
valid_sources[0x39]	6387	1			T4	1		T16	9		T20	1
valid_sources[0x3a]	5361	1			T16	7		T20	4		T21	3
valid_sources[0x3b]	5326	1			T15	2		T16	9		T20	4
valid_sources[0x3c]	5436	1			T15	3		T16	10		T5	6
valid_sources[0x3d]	6320	1			T4	1		T15	5		T16	5
valid_sources[0x3e]	32560	1			T15	2		T16	8		T20	6
valid_sources[0x3f]	5498	1			T15	3		T16	5		T5	16
valid_sources[0x40]	5374	1			T4	1		T15	3		T16	10
valid_sources[0x41]	5522	1			T15	4		T16	8		T20	4
valid_sources[0x42]	5272	1			T4	1		T15	1		T16	8
valid_sources[0x43]	5261	1			T15	5		T16	7		T20	3
valid_sources[0x44]	5697	1			T15	3		T16	5		T21	10
valid_sources[0x45]	5741	1			T4	1		T16	2		T20	2
valid_sources[0x46]	7889	1			T15	1		T16	11		T20	3
valid_sources[0x47]	5486	1			T4	3		T16	18		T20	4
valid_sources[0x48]	13512	1			T4	5		T15	1		T16	10
valid_sources[0x49]	4945	1			T16	15		T20	2		T21	11
valid_sources[0x4a]	5286	1			T16	7		T20	2		T21	5
valid_sources[0x4b]	5515	1			T4	1		T16	7		T20	5
valid_sources[0x4c]	4999	1			T15	3		T16	8		T5	3
valid_sources[0x4d]	13528	1			T15	4		T16	5		T20	4
valid_sources[0x4e]	5357	1			T4	1		T15	1		T16	5
valid_sources[0x4f]	5218	1			T16	9		T20	2		T21	7
valid_sources[0x50]	6056	1			T15	7		T16	8		T5	17
valid_sources[0x51]	5334	1			T16	8		T5	2		T20	5
valid_sources[0x52]	5444	1			T4	3		T15	5		T16	6
valid_sources[0x53]	5168	1			T16	6		T20	1		T8	2
valid_sources[0x54]	5339	1			T16	9		T20	4		T21	11
valid_sources[0x55]	5175	1			T15	4		T16	6		T20	2
valid_sources[0x56]	5650	1			T4	1		T16	5		T20	4
valid_sources[0x57]	6853	1			T15	9		T16	3		T5	3
valid_sources[0x58]	5065	1			T15	5		T16	7		T20	1
valid_sources[0x59]	5177	1			T16	7		T20	4		T21	5
valid_sources[0x5a]	5258	1			T11	3		T16	7		T20	2
valid_sources[0x5b]	6462	1			T15	2		T16	8		T20	2
valid_sources[0x5c]	5522	1			T12	1		T16	9		T20	4
valid_sources[0x5d]	5478	1			T16	10		T5	7		T20	2
valid_sources[0x5e]	5761	1			T4	1		T15	4		T16	10
valid_sources[0x5f]	8353	1			T4	2		T16	7		T21	6
valid_sources[0x60]	5709	1			T12	1		T16	10		T21	4
valid_sources[0x61]	5127	1			T15	7		T16	8		T20	2
valid_sources[0x62]	5299	1			T16	11		T20	5		T21	7
valid_sources[0x63]	6924	1			T4	1		T15	4		T16	5
valid_sources[0x64]	5854	1			T4	1		T15	1		T16	7
valid_sources[0x65]	7473	1			T4	2		T16	7		T20	4
valid_sources[0x66]	5213	1			T15	1		T16	7		T5	19
valid_sources[0x67]	6525	1			T15	3		T16	8		T20	2
valid_sources[0x68]	14146	1			T15	5		T16	9		T20	3
valid_sources[0x69]	7782	1			T12	1		T4	1		T16	5
valid_sources[0x6a]	5193	1			T4	3		T16	6		T20	2
valid_sources[0x6b]	8587	1			T15	1		T16	3		T20	2
valid_sources[0x6c]	5460	1			T16	8		T20	2		T21	3
valid_sources[0x6d]	5366	1			T15	2		T16	4		T5	11
valid_sources[0x6e]	5165	1			T4	2		T15	1		T16	7
valid_sources[0x6f]	5076	1			T4	1		T15	5		T16	5
valid_sources[0x70]	5286	1			T14	4		T16	11		T5	7
valid_sources[0x71]	6145	1			T15	1		T16	5		T20	2
valid_sources[0x72]	5569	1			T15	3		T16	6		T20	3
valid_sources[0x73]	5502	1			T12	1		T15	1		T16	6
valid_sources[0x74]	5839	1			T15	2		T16	7		T20	4
valid_sources[0x75]	11255	1			T4	1		T15	3		T16	8
valid_sources[0x76]	6388	1			T16	5		T20	2		T21	11
valid_sources[0x77]	5357	1			T15	2		T16	7		T20	1
valid_sources[0x78]	5461	1			T15	1		T16	7		T20	9
valid_sources[0x79]	5829	1			T15	2		T16	7		T20	2
valid_sources[0x7a]	7972	1			T4	1		T16	4		T20	6
valid_sources[0x7b]	5846	1			T4	3		T16	12		T20	2
valid_sources[0x7c]	5429	1			T15	3		T16	8		T20	2
valid_sources[0x7d]	9524	1			T15	1		T16	8		T20	1
valid_sources[0x7e]	5224	1			T15	3		T16	5		T20	6
valid_sources[0x7f]	5439	1			T4	4		T15	3		T16	5
valid_sources[0x80]	6534	1			T15	3		T16	10		T21	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

717107

1

T2

13

T3

116

T11

1

values[0x0]

all_enables

biggest_size

126375

1

T1

4

T2

3

T3

50

values[0x1]

all_enables

biggest_size

124600

1

T1

2

T2

3

T3

42