Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	64566336	14677	0	0
claim_transition_if_regwen_rd_A	64566336	1054	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64566336	14677	0	0
T69	22053	0	0	0
T105	166971	4	0	0
T108	138648	4	0	0
T109	0	4	0	0
T114	0	1	0	0
T115	0	3	0	0
T161	0	2	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	11	0	0
T165	0	3	0	0
T166	7931	0	0	0
T167	802	0	0	0
T168	218863	0	0	0
T169	56345	0	0	0
T170	30937	0	0	0
T171	47958	0	0	0
T172	91075	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64566336	1054	0	0
T86	1790	0	0	0
T115	245140	9	0	0
T120	0	41	0	0
T130	0	16	0	0
T140	0	18	0	0
T162	0	6	0	0
T173	0	16	0	0
T174	0	2	0	0
T175	0	8	0	0
T176	0	2	0	0
T177	0	2	0	0
T178	2006	0	0	0
T179	65144	0	0	0
T180	30543	0	0	0
T181	18422	0	0	0
T182	32061	0	0	0
T183	19513	0	0	0
T184	1261	0	0	0
T185	7570	0	0	0