Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	64339834	14202	0	0
claim_transition_if_regwen_rd_A	64339834	895	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64339834	14202	0	0
T100	181467	3	0	0
T101	0	15	0	0
T153	0	5	0	0
T154	0	5	0	0
T155	0	7	0	0
T156	0	4	0	0
T157	0	1	0	0
T158	0	4	0	0
T159	0	11	0	0
T160	0	2	0	0
T161	15071	0	0	0
T162	56793	0	0	0
T163	10659	0	0	0
T164	128225	0	0	0
T165	88371	0	0	0
T166	29309	0	0	0
T167	2754	0	0	0
T168	76973	0	0	0
T169	1193	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64339834	895	0	0
T102	143338	5	0	0
T118	0	30	0	0
T123	0	43	0	0
T149	0	5	0	0
T160	0	7	0	0
T170	0	2	0	0
T171	0	22	0	0
T172	0	1	0	0
T173	0	120	0	0
T174	0	1	0	0
T175	759	0	0	0
T176	294601	0	0	0
T177	29640	0	0	0
T178	38446	0	0	0
T179	396996	0	0	0
T180	316154	0	0	0
T181	126301	0	0	0
T182	18983	0	0	0
T183	6721	0	0	0