Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	983397	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1170783

1

T1

522

T2

5

T3

179

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1864704	1			T1	901		T2	7		T3	132
values[0x0]	144064	1			T1	49		T2	5		T3	76
values[0x1]	145412	1			T1	46		T2	3		T3	68

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	779351	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1374829

1

T1

617

T2

8

T3

197

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5733	1			T4	5		T13	4		T14	1
valid_sources[0x01]	7493	1			T13	6		T14	14		T16	14
valid_sources[0x02]	7030	1			T13	3		T14	5		T16	18
valid_sources[0x03]	5926	1			T4	2		T13	4		T14	11
valid_sources[0x04]	5801	1			T13	10		T14	21		T16	12
valid_sources[0x05]	5945	1			T4	6		T13	9		T14	2
valid_sources[0x06]	6398	1			T4	1		T13	4		T14	5
valid_sources[0x07]	51728	1			T4	1		T13	5		T14	8
valid_sources[0x08]	6161	1			T13	12		T14	8		T16	11
valid_sources[0x09]	6022	1			T13	3		T14	23		T16	14
valid_sources[0x0a]	6127	1			T4	2		T13	5		T14	18
valid_sources[0x0b]	6084	1			T13	5		T16	11		T8	1
valid_sources[0x0c]	5664	1			T13	5		T14	17		T16	15
valid_sources[0x0d]	6790	1			T13	12		T14	5		T16	9
valid_sources[0x0e]	40965	1			T4	3		T13	11		T14	17
valid_sources[0x0f]	5954	1			T13	1		T14	5		T16	14
valid_sources[0x10]	6019	1			T13	3		T14	12		T16	20
valid_sources[0x11]	6503	1			T13	4		T14	13		T16	7
valid_sources[0x12]	6174	1			T13	15		T14	15		T16	15
valid_sources[0x13]	8319	1			T13	4		T14	3		T16	11
valid_sources[0x14]	5914	1			T4	2		T13	4		T14	9
valid_sources[0x15]	5870	1			T13	2		T14	11		T16	8
valid_sources[0x16]	6092	1			T13	7		T14	15		T16	11
valid_sources[0x17]	6726	1			T13	3		T14	8		T16	15
valid_sources[0x18]	6324	1			T13	10		T16	17		T20	11
valid_sources[0x19]	5814	1			T4	4		T13	1		T14	12
valid_sources[0x1a]	6494	1			T4	3		T13	1		T14	9
valid_sources[0x1b]	8755	1			T13	6		T14	9		T16	12
valid_sources[0x1c]	6069	1			T13	6		T14	12		T16	15
valid_sources[0x1d]	6006	1			T13	3		T14	18		T16	10
valid_sources[0x1e]	5707	1			T13	3		T14	19		T16	10
valid_sources[0x1f]	5686	1			T13	7		T14	21		T16	20
valid_sources[0x20]	7537	1			T13	7		T14	10		T16	12
valid_sources[0x21]	5740	1			T13	8		T14	8		T16	9
valid_sources[0x22]	7963	1			T13	4		T14	27		T16	18
valid_sources[0x23]	114290	1			T13	4		T14	15		T16	18
valid_sources[0x24]	7491	1			T13	5		T14	5		T16	16
valid_sources[0x25]	5813	1			T13	6		T14	9		T16	11
valid_sources[0x26]	8317	1			T13	5		T14	12		T16	11
valid_sources[0x27]	5698	1			T4	1		T13	7		T14	1
valid_sources[0x28]	6046	1			T4	6		T13	6		T14	18
valid_sources[0x29]	5607	1			T13	8		T14	13		T15	1
valid_sources[0x2a]	6065	1			T13	8		T14	13		T16	9
valid_sources[0x2b]	5972	1			T13	11		T14	2		T16	22
valid_sources[0x2c]	11020	1			T2	1		T13	9		T14	6
valid_sources[0x2d]	6933	1			T13	15		T14	12		T16	18
valid_sources[0x2e]	6093	1			T13	9		T14	18		T16	12
valid_sources[0x2f]	8715	1			T13	6		T14	11		T16	16
valid_sources[0x30]	6059	1			T13	4		T14	1		T16	12
valid_sources[0x31]	8696	1			T4	2		T13	2		T14	5
valid_sources[0x32]	7129	1			T13	7		T14	19		T16	11
valid_sources[0x33]	9361	1			T13	4		T14	1		T16	20
valid_sources[0x34]	6858	1			T13	3		T14	12		T16	14
valid_sources[0x35]	8453	1			T4	2		T13	7		T14	4
valid_sources[0x36]	5871	1			T4	1		T13	1		T14	13
valid_sources[0x37]	6533	1			T13	4		T14	5		T16	7
valid_sources[0x38]	5669	1			T13	7		T14	10		T16	17
valid_sources[0x39]	5844	1			T4	2		T13	7		T14	7
valid_sources[0x3a]	5648	1			T13	5		T14	13		T16	9
valid_sources[0x3b]	9534	1			T4	1		T13	4		T14	9
valid_sources[0x3c]	6801	1			T13	10		T14	15		T16	21
valid_sources[0x3d]	8115	1			T13	5		T14	14		T16	11
valid_sources[0x3e]	5849	1			T13	9		T14	9		T16	12
valid_sources[0x3f]	10352	1			T4	1		T13	5		T14	11
valid_sources[0x40]	7112	1			T13	6		T14	8		T16	12
valid_sources[0x41]	6357	1			T13	7		T14	9		T16	10
valid_sources[0x42]	6039	1			T4	1		T13	5		T14	6
valid_sources[0x43]	5971	1			T13	10		T14	9		T16	14
valid_sources[0x44]	8097	1			T13	3		T14	21		T16	13
valid_sources[0x45]	5951	1			T4	6		T13	9		T14	13
valid_sources[0x46]	5584	1			T13	4		T14	15		T16	16
valid_sources[0x47]	7601	1			T3	276		T13	9		T14	23
valid_sources[0x48]	6122	1			T4	7		T13	4		T14	5
valid_sources[0x49]	17222	1			T4	4		T13	3		T14	15
valid_sources[0x4a]	5903	1			T4	1		T13	10		T14	14
valid_sources[0x4b]	5963	1			T4	7		T13	3		T14	18
valid_sources[0x4c]	5993	1			T13	4		T14	11		T16	9
valid_sources[0x4d]	6013	1			T13	10		T14	6		T16	15
valid_sources[0x4e]	5996	1			T13	11		T14	16		T16	11
valid_sources[0x4f]	5962	1			T13	4		T14	5		T16	15
valid_sources[0x50]	6260	1			T4	3		T13	10		T14	14
valid_sources[0x51]	5822	1			T2	1		T13	6		T14	7
valid_sources[0x52]	6542	1			T13	6		T14	8		T15	1
valid_sources[0x53]	6152	1			T13	8		T14	24		T16	9
valid_sources[0x54]	6240	1			T13	5		T14	4		T16	15
valid_sources[0x55]	7044	1			T4	3		T13	10		T14	3
valid_sources[0x56]	8020	1			T13	7		T14	4		T16	19
valid_sources[0x57]	7407	1			T13	5		T14	6		T16	10
valid_sources[0x58]	5850	1			T13	8		T14	2		T16	9
valid_sources[0x59]	5965	1			T2	1		T13	5		T14	3
valid_sources[0x5a]	8894	1			T1	996		T13	2		T14	8
valid_sources[0x5b]	6116	1			T2	1		T13	8		T14	15
valid_sources[0x5c]	6129	1			T2	1		T13	7		T14	23
valid_sources[0x5d]	7566	1			T13	5		T14	25		T16	16
valid_sources[0x5e]	6515	1			T13	5		T14	17		T16	7
valid_sources[0x5f]	5930	1			T4	2		T13	7		T14	4
valid_sources[0x60]	5899	1			T13	2		T14	6		T16	14
valid_sources[0x61]	5786	1			T4	4		T13	10		T14	9
valid_sources[0x62]	6837	1			T13	7		T14	10		T16	12
valid_sources[0x63]	6549	1			T13	1		T14	11		T16	18
valid_sources[0x64]	5811	1			T4	2		T13	5		T14	28
valid_sources[0x65]	6142	1			T4	1		T13	5		T14	5
valid_sources[0x66]	6373	1			T13	13		T14	7		T16	16
valid_sources[0x67]	7183	1			T13	9		T16	13		T20	3
valid_sources[0x68]	7702	1			T13	9		T14	1		T16	18
valid_sources[0x69]	6045	1			T13	7		T14	5		T16	9
valid_sources[0x6a]	7720	1			T13	8		T14	3		T16	15
valid_sources[0x6b]	6513	1			T4	1		T13	3		T14	11
valid_sources[0x6c]	110850	1			T13	5		T14	6		T16	10
valid_sources[0x6d]	6138	1			T4	4		T13	16		T14	10
valid_sources[0x6e]	7048	1			T13	5		T14	9		T16	14
valid_sources[0x6f]	5881	1			T13	5		T14	20		T15	1
valid_sources[0x70]	6340	1			T13	11		T14	14		T16	7
valid_sources[0x71]	10304	1			T13	4		T14	7		T16	10
valid_sources[0x72]	5927	1			T13	1		T14	8		T16	16
valid_sources[0x73]	5794	1			T2	2		T13	12		T14	6
valid_sources[0x74]	8241	1			T4	2		T13	15		T14	13
valid_sources[0x75]	5990	1			T13	5		T14	15		T16	12
valid_sources[0x76]	5950	1			T4	3		T13	5		T14	17
valid_sources[0x77]	7101	1			T2	1		T4	2		T13	2
valid_sources[0x78]	6853	1			T4	2		T13	4		T14	9
valid_sources[0x79]	6082	1			T13	4		T14	12		T16	12
valid_sources[0x7a]	6060	1			T13	9		T14	23		T16	17
valid_sources[0x7b]	7302	1			T13	6		T14	8		T16	15
valid_sources[0x7c]	5999	1			T13	9		T14	16		T16	23
valid_sources[0x7d]	6187	1			T13	8		T14	3		T16	24
valid_sources[0x7e]	6094	1			T13	6		T14	17		T16	11
valid_sources[0x7f]	5729	1			T13	11		T14	3		T16	14
valid_sources[0x80]	5997	1			T4	3		T13	8		T14	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

922323

1

T1

444

T3

56

T4

75

values[0x0]

all_enables

biggest_size

124555

1

T1

40

T2

3

T3

68

values[0x1]

all_enables

biggest_size

123905

1

T1

38

T2

2

T3

55