Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2055843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2290358

1

T1

5

T2

167

T3

193

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3978511	1			T1	2		T2	218		T3	284
values[0x0]	183780	1			T1	2		T2	40		T3	35
values[0x1]	183910	1			T1	6		T2	29		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1634136	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2712065

1

T1

5

T2

199

T3

225

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12560	1			T4	1		T12	1		T21	7
valid_sources[0x01]	14314	1			T3	5		T4	1		T12	4
valid_sources[0x02]	12266	1			T3	4		T4	1		T12	6
valid_sources[0x03]	11826	1			T4	1		T12	4		T21	4
valid_sources[0x04]	21858	1			T3	5		T12	4		T15	1
valid_sources[0x05]	12319	1			T3	3		T4	2		T12	5
valid_sources[0x06]	28042	1			T4	2		T12	4		T14	1
valid_sources[0x07]	13549	1			T3	2		T4	5		T12	4
valid_sources[0x08]	12257	1			T3	1		T4	1		T12	6
valid_sources[0x09]	12637	1			T3	2		T4	1		T12	5
valid_sources[0x0a]	11588	1			T3	1		T4	1		T12	3
valid_sources[0x0b]	29490	1			T3	2		T4	5		T12	2
valid_sources[0x0c]	13038	1			T3	1		T4	2		T12	5
valid_sources[0x0d]	13369	1			T4	2		T12	2		T14	1
valid_sources[0x0e]	13804	1			T3	3		T4	1		T12	5
valid_sources[0x0f]	12309	1			T3	1		T4	2		T12	4
valid_sources[0x10]	24796	1			T3	3		T4	1		T12	4
valid_sources[0x11]	12231	1			T12	6		T15	2		T21	6
valid_sources[0x12]	23797	1			T4	3		T12	6		T15	1
valid_sources[0x13]	15620	1			T3	3		T4	3		T12	6
valid_sources[0x14]	12576	1			T3	2		T12	1		T15	1
valid_sources[0x15]	21248	1			T3	2		T12	2		T15	1
valid_sources[0x16]	17693	1			T4	2		T12	5		T14	1
valid_sources[0x17]	29292	1			T3	3		T12	3		T14	1
valid_sources[0x18]	12520	1			T3	1		T4	3		T12	6
valid_sources[0x19]	242896	1			T4	3		T12	2		T15	1
valid_sources[0x1a]	17306	1			T12	7		T24	17		T31	1
valid_sources[0x1b]	11789	1			T3	3		T4	2		T12	3
valid_sources[0x1c]	12185	1			T3	2		T4	1		T12	1
valid_sources[0x1d]	12030	1			T3	1		T4	1		T12	4
valid_sources[0x1e]	12648	1			T4	3		T12	4		T21	7
valid_sources[0x1f]	12124	1			T3	1		T4	1		T12	4
valid_sources[0x20]	12857	1			T4	4		T12	5		T14	2
valid_sources[0x21]	12210	1			T4	1		T12	7		T15	2
valid_sources[0x22]	13602	1			T3	2		T12	5		T21	11
valid_sources[0x23]	11908	1			T3	4		T12	2		T15	5
valid_sources[0x24]	12039	1			T3	3		T4	1		T15	3
valid_sources[0x25]	12022	1			T3	3		T12	3		T21	1
valid_sources[0x26]	12137	1			T3	1		T4	3		T12	5
valid_sources[0x27]	18108	1			T3	1		T4	1		T12	5
valid_sources[0x28]	13518	1			T3	3		T4	1		T12	5
valid_sources[0x29]	12312	1			T3	4		T4	1		T12	2
valid_sources[0x2a]	12134	1			T3	3		T12	6		T14	1
valid_sources[0x2b]	12235	1			T3	1		T12	5		T14	1
valid_sources[0x2c]	12078	1			T3	3		T12	1		T21	5
valid_sources[0x2d]	15395	1			T3	1		T4	3		T12	4
valid_sources[0x2e]	11944	1			T3	2		T4	2		T12	5
valid_sources[0x2f]	12119	1			T4	2		T12	5		T15	2
valid_sources[0x30]	12481	1			T3	2		T4	5		T12	4
valid_sources[0x31]	11902	1			T3	1		T12	3		T21	2
valid_sources[0x32]	11742	1			T3	1		T4	1		T12	1
valid_sources[0x33]	11657	1			T3	2		T4	1		T12	5
valid_sources[0x34]	11954	1			T3	1		T12	6		T15	2
valid_sources[0x35]	12024	1			T4	3		T12	4		T21	6
valid_sources[0x36]	49143	1			T3	3		T12	4		T15	4
valid_sources[0x37]	12474	1			T4	2		T12	3		T21	6
valid_sources[0x38]	11931	1			T3	2		T4	2		T12	5
valid_sources[0x39]	12625	1			T3	1		T4	1		T12	7
valid_sources[0x3a]	11898	1			T4	1		T12	4		T14	1
valid_sources[0x3b]	12272	1			T3	1		T4	1		T12	2
valid_sources[0x3c]	12242	1			T3	1		T4	1		T12	3
valid_sources[0x3d]	11592	1			T3	1		T4	2		T12	6
valid_sources[0x3e]	16654	1			T3	2		T4	2		T12	4
valid_sources[0x3f]	14194	1			T3	2		T4	2		T12	5
valid_sources[0x40]	13664	1			T3	6		T4	4		T12	6
valid_sources[0x41]	88162	1			T4	1		T12	3		T21	1
valid_sources[0x42]	11731	1			T3	1		T4	1		T12	5
valid_sources[0x43]	13192	1			T3	1		T12	5		T15	1
valid_sources[0x44]	13844	1			T4	3		T12	2		T15	2
valid_sources[0x45]	12250	1			T3	2		T4	3		T12	1
valid_sources[0x46]	12217	1			T3	2		T12	1		T21	9
valid_sources[0x47]	11965	1			T3	1		T4	1		T12	1
valid_sources[0x48]	11806	1			T3	2		T12	1		T16	8
valid_sources[0x49]	11905	1			T4	2		T12	4		T21	8
valid_sources[0x4a]	11952	1			T3	1		T12	1		T21	2
valid_sources[0x4b]	11980	1			T3	1		T12	1		T21	10
valid_sources[0x4c]	12199	1			T3	4		T4	4		T12	5
valid_sources[0x4d]	12090	1			T12	1		T24	17		T21	3
valid_sources[0x4e]	12018	1			T1	10		T3	2		T4	1
valid_sources[0x4f]	40455	1			T3	3		T4	2		T12	2
valid_sources[0x50]	11938	1			T3	1		T4	1		T12	5
valid_sources[0x51]	12309	1			T3	2		T4	2		T12	2
valid_sources[0x52]	12015	1			T4	3		T12	2		T15	1
valid_sources[0x53]	12252	1			T3	1		T4	2		T12	4
valid_sources[0x54]	18290	1			T3	2		T12	2		T15	2
valid_sources[0x55]	12636	1			T3	1		T4	3		T12	2
valid_sources[0x56]	40465	1			T3	2		T12	4		T21	2
valid_sources[0x57]	12378	1			T3	1		T4	2		T12	2
valid_sources[0x58]	14657	1			T3	2		T4	4		T12	7
valid_sources[0x59]	13512	1			T3	1		T4	1		T12	3
valid_sources[0x5a]	25159	1			T3	3		T12	2		T15	1
valid_sources[0x5b]	18014	1			T3	1		T4	1		T12	2
valid_sources[0x5c]	14475	1			T4	2		T12	5		T14	1
valid_sources[0x5d]	11907	1			T4	3		T12	5		T21	5
valid_sources[0x5e]	11725	1			T3	5		T4	1		T12	4
valid_sources[0x5f]	12418	1			T3	3		T4	1		T12	4
valid_sources[0x60]	12505	1			T3	2		T12	3		T21	5
valid_sources[0x61]	12072	1			T3	2		T12	3		T15	2
valid_sources[0x62]	12449	1			T3	4		T12	6		T21	3
valid_sources[0x63]	12578	1			T4	1		T12	2		T14	3
valid_sources[0x64]	12147	1			T4	1		T12	5		T21	6
valid_sources[0x65]	19449	1			T3	2		T12	3		T21	5
valid_sources[0x66]	12271	1			T4	1		T12	2		T15	5
valid_sources[0x67]	17481	1			T3	2		T4	1		T12	3
valid_sources[0x68]	12732	1			T3	1		T12	5		T15	2
valid_sources[0x69]	12845	1			T4	3		T12	7		T21	10
valid_sources[0x6a]	12266	1			T3	3		T4	2		T12	3
valid_sources[0x6b]	12339	1			T12	1		T15	1		T21	2
valid_sources[0x6c]	12105	1			T3	2		T4	1		T12	3
valid_sources[0x6d]	12196	1			T4	1		T12	2		T31	2
valid_sources[0x6e]	11881	1			T4	1		T12	1		T21	2
valid_sources[0x6f]	12201	1			T12	2		T15	1		T21	5
valid_sources[0x70]	12197	1			T3	1		T4	1		T21	2
valid_sources[0x71]	13281	1			T3	4		T12	3		T21	11
valid_sources[0x72]	12160	1			T3	1		T4	2		T12	4
valid_sources[0x73]	13354	1			T3	2		T4	1		T12	4
valid_sources[0x74]	12296	1			T2	287		T12	6		T21	7
valid_sources[0x75]	12305	1			T3	1		T12	6		T15	1
valid_sources[0x76]	12308	1			T4	5		T12	1		T15	4
valid_sources[0x77]	11934	1			T3	1		T12	4		T21	1
valid_sources[0x78]	12243	1			T4	4		T12	2		T14	2
valid_sources[0x79]	12303	1			T3	2		T4	2		T12	6
valid_sources[0x7a]	12100	1			T3	2		T4	3		T12	4
valid_sources[0x7b]	12873	1			T4	2		T12	2		T15	2
valid_sources[0x7c]	11937	1			T3	7		T12	7		T14	1
valid_sources[0x7d]	12119	1			T3	1		T12	6		T21	6
valid_sources[0x7e]	13660	1			T4	1		T12	1		T14	1
valid_sources[0x7f]	16279	1			T12	2		T14	1		T21	9
valid_sources[0x80]	12183	1			T12	2		T15	1		T21	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1973319

1

T2

109

T3

145

T4

84

values[0x0]

all_enables

biggest_size

159471

1

T1

2

T2

32

T3

30

values[0x1]

all_enables

biggest_size

157568

1

T1

3

T2

26

T3

18