Unified Coverage Report :: Module :: dmi_cdc

Module : dmi_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.95			73.95

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_cdc	74.30			74.30

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.30			74.30

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.38			81.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
74.78			74.78				u_dmi_jtag

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_cdc_req	75.24			75.24
i_cdc_resp	97.86			97.86
u_combined_rstn_sync	100.00			100.00
u_rst_mux	75.00			75.00

Toggle Coverage for Module : dmi_cdc

	Total	Covered	Percent
Totals	25	20	80.00
Total Bits	430	318	73.95
Total Bits 0->1	215	159	73.95
Total Bits 1->0	215	159	73.95

Ports	25	20	80.00
Port Bits	430	318	73.95
Port Bits 0->1	215	159	73.95
Port Bits 1->0	215	159	73.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
testmode_i	No	No		No		INPUT
test_rst_ni	Yes	Yes	T8,T9,T10	Yes	T8,T9,T11	INPUT
tck_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
trst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
jtag_dmi_req_i.data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
jtag_dmi_req_i.op[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
jtag_dmi_req_i.addr[6:0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
jtag_dmi_req_i.addr[31:7]	No	No		No		INPUT
jtag_dmi_ready_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
jtag_dmi_valid_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
jtag_dmi_cdc_clear_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
jtag_dmi_resp_o.resp[1:0]	No	No		No		OUTPUT
jtag_dmi_resp_o.data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
jtag_dmi_valid_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
jtag_dmi_ready_i	Unreachable	Unreachable		Unreachable		INPUT
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
core_dmi_rst_no	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_req_o.data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_req_o.op[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_req_o.addr[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_req_o.addr[31:6]	No	No		No		OUTPUT
core_dmi_valid_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_ready_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
core_dmi_resp_i.resp[1:0]	No	No		No		INPUT
core_dmi_resp_i.data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
core_dmi_ready_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_valid_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc

	Total	Covered	Percent
Totals	25	20	80.00
Total Bits	428	318	74.30
Total Bits 0->1	213	159	74.65
Total Bits 1->0	215	159	73.95

Ports	25	20	80.00
Port Bits	428	318	74.30
Port Bits 0->1	213	159	74.65
Port Bits 1->0	215	159	73.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
testmode_i	No	No		No		INPUT
test_rst_ni	Yes	Yes	T8,T9,T10	Yes	T8,T9,T11	INPUT
tck_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
trst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
jtag_dmi_req_i.data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
jtag_dmi_req_i.op[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
jtag_dmi_req_i.addr[6:0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
jtag_dmi_req_i.addr[31:7]	No	No		No		INPUT
jtag_dmi_ready_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
jtag_dmi_valid_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
jtag_dmi_cdc_clear_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
jtag_dmi_resp_o.resp[1:0]	No	No		Excluded		OUTPUT	0->1:VC_COV_UNR
jtag_dmi_resp_o.data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
jtag_dmi_valid_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
jtag_dmi_ready_i	Unreachable	Unreachable		Unreachable		INPUT
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
core_dmi_rst_no	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_req_o.data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_req_o.op[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_req_o.addr[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_req_o.addr[31:6]	No	No		No		OUTPUT
core_dmi_valid_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_ready_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
core_dmi_resp_i.resp[1:0]	No	No		No		INPUT
core_dmi_resp_i.data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
core_dmi_ready_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_dmi_valid_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT

*Tests covering at least one bit in the range