Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00
tb.dut.u_reg_tap.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00

Ports	5	5	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
oh_i[0]	Yes	Yes	*T32,*T61,*T98	Yes	T32,T61,T98	INPUT
oh_i[1]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[3:2]	Yes	Yes	T61,*T62,*T63	Yes	T61,T62,T63	INPUT
oh_i[4]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[12:5]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[34:13]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
err_o	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00

Ports	5	5	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
oh_i[0]	Yes	Yes	*T32,*T61,*T98	Yes	T32,T61,T98	INPUT
oh_i[1]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[3:2]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
oh_i[4]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[12:5]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[34:13]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
err_o	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_tap.u_prim_reg_we_check.u_prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00

Ports	5	5	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
oh_i[0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
oh_i[1]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[3:2]	Yes	Yes	T61,*T62,*T63	Yes	T61,T62,T63	INPUT
oh_i[4]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[12:5]	Yes	Yes	T5,*T6,*T7	Yes	T5,T6,T7	INPUT
oh_i[34:13]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
err_o	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT

*Tests covering at least one bit in the range