Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	117401664	15098	0	0
claim_transition_if_regwen_rd_A	117401664	976	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117401664	15098	0	0
T101	141156	1	0	0
T102	166050	3	0	0
T117	0	9	0	0
T118	0	5	0	0
T122	0	13	0	0
T159	0	3	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	2	0	0
T163	0	2	0	0
T164	7455	0	0	0
T165	60888	0	0	0
T166	27071	0	0	0
T167	5426	0	0	0
T168	30972	0	0	0
T169	1630	0	0	0
T170	21906	0	0	0
T171	18785	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117401664	976	0	0
T101	141156	4	0	0
T102	166050	0	0	0
T119	0	19	0	0
T120	0	91	0	0
T121	0	3	0	0
T157	0	11	0	0
T159	0	9	0	0
T164	7455	0	0	0
T165	60888	0	0	0
T166	27071	0	0	0
T167	5426	0	0	0
T168	30972	0	0	0
T169	1630	0	0	0
T170	21906	0	0	0
T171	18785	0	0	0
T172	0	6	0	0
T173	0	9	0	0
T174	0	4	0	0
T175	0	1	0	0