Line Coverage for Module :
lc_ctrl_state_transition
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 66 | 64 | 96.97 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| ALWAYS | 52 | 65 | 63 | 96.92 |
44 logic unused_trans_cmd;
45 1/1 assign unused_trans_cmd = trans_cmd_i;
Tests: T1 T2 T3
46 end
47
48 // The decoder logic below checks whether a given transition edge
49 // is valid and computes the next lc counter ans state vectors.
50 always_comb begin : p_lc_state_transition
51 // Decoded state defaults
52 1/1 next_lc_cnt_o = lc_cnt_i;
Tests: T1 T2 T3
53 1/1 next_lc_state_o = lc_state_i;
Tests: T1 T2 T3
54 1/1 trans_cnt_oflw_error_o = 1'b0;
Tests: T1 T2 T3
55 1/1 trans_invalid_error_o = 1'b0;
Tests: T1 T2 T3
56
57 // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
58 // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
59 // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
60 // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
61 // ---------------------------------------------------------------
62 // Only enter here if volatile RAW unlock is available and enabled.
63 1/1 if (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i && fsm_state_i == IdleSt)
Tests: T1 T2 T3
64 begin
65 // We only allow transitions from RAW -> TEST_UNLOCKED0
66 unreachable if (dec_lc_state_i != {DecLcStateNumRep{DecLcStRaw}} ||
67 trans_target_i != {DecLcStateNumRep{DecLcStTestUnlocked0}}) begin
68 unreachable trans_invalid_error_o = 1'b1;
69 end
==> MISSING_ELSE
70 end
MISSING_ELSE
71 // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
72
73 1/1 if (fsm_state_i inside {CntIncrSt,
Tests: T1 T2 T3
74 CntProgSt,
75 // Since OTP programming is incremental, we have to keep the next
76 // counter state assigned when performing the actual state transition
77 // in the second programming pass to prevent OTP programming errors.
78 TransCheckSt,
79 TokenCheck0St,
80 TokenCheck1St,
81 TransProgSt}) begin
82 // In this state, the life cycle counter is incremented.
83 // Throw an error if the counter is already maxed out.
84 1/1 unique case (lc_cnt_i)
Tests: T1 T2 T3
85 1/1 LcCnt0: next_lc_cnt_o = LcCnt1;
Tests: T17 T18 T19
86 1/1 LcCnt1: next_lc_cnt_o = LcCnt2;
Tests: T1 T3 T13
87 1/1 LcCnt2: next_lc_cnt_o = LcCnt3;
Tests: T1 T13 T14
88 1/1 LcCnt3: next_lc_cnt_o = LcCnt4;
Tests: T1 T4 T13
89 1/1 LcCnt4: next_lc_cnt_o = LcCnt5;
Tests: T4 T13 T14
90 1/1 LcCnt5: next_lc_cnt_o = LcCnt6;
Tests: T3 T13 T14
91 1/1 LcCnt6: next_lc_cnt_o = LcCnt7;
Tests: T3 T4 T13
92 1/1 LcCnt7: next_lc_cnt_o = LcCnt8;
Tests: T1 T4 T13
93 1/1 LcCnt8: next_lc_cnt_o = LcCnt9;
Tests: T1 T13 T14
94 1/1 LcCnt9: next_lc_cnt_o = LcCnt10;
Tests: T1 T13 T14
95 1/1 LcCnt10: next_lc_cnt_o = LcCnt11;
Tests: T1 T4 T13
96 1/1 LcCnt11: next_lc_cnt_o = LcCnt12;
Tests: T4 T14 T16
97 1/1 LcCnt12: next_lc_cnt_o = LcCnt13;
Tests: T3 T4 T13
98 1/1 LcCnt13: next_lc_cnt_o = LcCnt14;
Tests: T3 T4 T13
99 1/1 LcCnt14: next_lc_cnt_o = LcCnt15;
Tests: T13 T14 T16
100 1/1 LcCnt15: next_lc_cnt_o = LcCnt16;
Tests: T13 T14 T16
101 1/1 LcCnt16: next_lc_cnt_o = LcCnt17;
Tests: T14 T20 T21
102 1/1 LcCnt17: next_lc_cnt_o = LcCnt18;
Tests: T4 T13 T14
103 1/1 LcCnt18: next_lc_cnt_o = LcCnt19;
Tests: T13 T17 T20
104 1/1 LcCnt19: next_lc_cnt_o = LcCnt20;
Tests: T13 T14 T6
105 1/1 LcCnt20: next_lc_cnt_o = LcCnt21;
Tests: T1 T13 T14
106 1/1 LcCnt21: next_lc_cnt_o = LcCnt22;
Tests: T13 T14 T6
107 1/1 LcCnt22: next_lc_cnt_o = LcCnt23;
Tests: T1 T2 T4
108 1/1 LcCnt23: next_lc_cnt_o = LcCnt24;
Tests: T13 T14 T16
109 1/1 LcCnt24: trans_cnt_oflw_error_o = 1'b1;
Tests: T13 T17 T22
110 default: trans_cnt_oflw_error_o = 1'b1;
111 endcase // lc_cnt_i
112
113 // We always allow transitions into the SCRAP state, so the overflow error is silenced in that
114 // particular case. In that case we max out the transition counter and force the
115 // next_lc_state already into SCRAP so that the error silencing above cannot be abused. This
116 // means that when moving to SCRAP state, we program LcStScrap twice: once during the counter
117 // increment phase, and once during the actual state programming phase.
118 1/1 if (trans_target_i == {DecLcStateNumRep{DecLcStScrap}}) begin
Tests: T1 T2 T3
119 1/1 next_lc_cnt_o = LcCnt24;
Tests: T1 T4 T13
120 1/1 next_lc_state_o = LcStScrap;
Tests: T1 T4 T13
121 1/1 trans_cnt_oflw_error_o = 1'b0;
Tests: T1 T4 T13
122 end
MISSING_ELSE
123 end
MISSING_ELSE
124
125 1/1 if (fsm_state_i inside {TransCheckSt,
Tests: T1 T2 T3
126 TokenCheck0St,
127 TokenCheck1St,
128 TransProgSt}) begin
129 // SEC_CM: STATE.CONFIG.SPARSE
130 // Check that the decoded transition indexes are valid before indexing the state transition
131 // matrix. We perform the check twice with different indices into the replicated state
132 // enumeration.
133 1/1 if (dec_lc_state_i[0] <= DecLcStScrap &&
Tests: T1 T2 T3
134 trans_target_i[0] <= DecLcStScrap &&
135 dec_lc_state_i[1] <= DecLcStScrap &&
136 trans_target_i[1] <= DecLcStScrap) begin
137 // Check the state transition token matrix in order to see whether this transition is valid.
138 // All transitions have a token index value different from InvalidTokenIdx. We perform the
139 // check twice with different indices into the replicated state enumeration.
140 1/1 if (TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx ||
Tests: T1 T2 T3
141 TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx) begin
142 // Encode the target state.
143 // Note that the life cycle encoding itself also ensures that only certain transitions are
144 // possible. So even if this logic here is tampered with, the encoding values won't allow
145 // an invalid transition (instead, the programming operation will fail and leave the life
146 // cycle state corrupted/invalid).
147 1/1 unique case (trans_target_i)
Tests: T1 T2 T3
148 0/1 ==> {DecLcStateNumRep{DecLcStRaw}}: next_lc_state_o = LcStRaw;
149 1/1 {DecLcStateNumRep{DecLcStTestUnlocked0}}: next_lc_state_o = LcStTestUnlocked0;
Tests: T2 T23 T24
150 1/1 {DecLcStateNumRep{DecLcStTestLocked0}}: next_lc_state_o = LcStTestLocked0;
Tests: T14 T21 T25
151 1/1 {DecLcStateNumRep{DecLcStTestUnlocked1}}: next_lc_state_o = LcStTestUnlocked1;
Tests: T20 T22 T24
152 1/1 {DecLcStateNumRep{DecLcStTestLocked1}}: next_lc_state_o = LcStTestLocked1;
Tests: T1 T13 T20
153 1/1 {DecLcStateNumRep{DecLcStTestUnlocked2}}: next_lc_state_o = LcStTestUnlocked2;
Tests: T3 T13 T20
154 1/1 {DecLcStateNumRep{DecLcStTestLocked2}}: next_lc_state_o = LcStTestLocked2;
Tests: T1 T13 T14
155 1/1 {DecLcStateNumRep{DecLcStTestUnlocked3}}: next_lc_state_o = LcStTestUnlocked3;
Tests: T14 T24 T26
156 1/1 {DecLcStateNumRep{DecLcStTestLocked3}}: next_lc_state_o = LcStTestLocked3;
Tests: T1 T13 T17
157 1/1 {DecLcStateNumRep{DecLcStTestUnlocked4}}: next_lc_state_o = LcStTestUnlocked4;
Tests: T14 T16 T20
158 1/1 {DecLcStateNumRep{DecLcStTestLocked4}}: next_lc_state_o = LcStTestLocked4;
Tests: T13 T5 T20
159 1/1 {DecLcStateNumRep{DecLcStTestUnlocked5}}: next_lc_state_o = LcStTestUnlocked5;
Tests: T13 T14 T16
160 1/1 {DecLcStateNumRep{DecLcStTestLocked5}}: next_lc_state_o = LcStTestLocked5;
Tests: T5 T20 T21
161 1/1 {DecLcStateNumRep{DecLcStTestUnlocked6}}: next_lc_state_o = LcStTestUnlocked6;
Tests: T3 T14 T17
162 1/1 {DecLcStateNumRep{DecLcStTestLocked6}}: next_lc_state_o = LcStTestLocked6;
Tests: T13 T20 T21
163 1/1 {DecLcStateNumRep{DecLcStTestUnlocked7}}: next_lc_state_o = LcStTestUnlocked7;
Tests: T16 T17 T20
164 1/1 {DecLcStateNumRep{DecLcStDev}}: next_lc_state_o = LcStDev;
Tests: T3 T13 T14
165 1/1 {DecLcStateNumRep{DecLcStProd}}: next_lc_state_o = LcStProd;
Tests: T1 T3 T13
166 1/1 {DecLcStateNumRep{DecLcStProdEnd}}: next_lc_state_o = LcStProdEnd;
Tests: T13 T14 T16
167 1/1 {DecLcStateNumRep{DecLcStRma}}: next_lc_state_o = LcStRma;
Tests: T1 T13 T14
168 1/1 {DecLcStateNumRep{DecLcStScrap}}: next_lc_state_o = LcStScrap;
Tests: T1 T13 T14
169 default: trans_invalid_error_o = 1'b1;
170 endcase // trans_target_i
171 end else begin
172 1/1 trans_invalid_error_o = 1'b1;
Tests: T13 T22 T27
173 end
174 end else begin
175 0/1 ==> trans_invalid_error_o = 1'b1;
176 end
177
178 // SEC_CM: STATE.CONFIG.SPARSE
179 // Check that the internally re-encoded life cycle state has a correct encoding.
180 1/1 unique case (dec_lc_state_i)
Tests: T1 T2 T3
181 {DecLcStateNumRep{DecLcStRaw}},
182 {DecLcStateNumRep{DecLcStTestUnlocked0}},
183 {DecLcStateNumRep{DecLcStTestLocked0}},
184 {DecLcStateNumRep{DecLcStTestUnlocked1}},
185 {DecLcStateNumRep{DecLcStTestLocked1}},
186 {DecLcStateNumRep{DecLcStTestUnlocked2}},
187 {DecLcStateNumRep{DecLcStTestLocked2}},
188 {DecLcStateNumRep{DecLcStTestUnlocked3}},
189 {DecLcStateNumRep{DecLcStTestLocked3}},
190 {DecLcStateNumRep{DecLcStTestUnlocked4}},
191 {DecLcStateNumRep{DecLcStTestLocked4}},
192 {DecLcStateNumRep{DecLcStTestUnlocked5}},
193 {DecLcStateNumRep{DecLcStTestLocked5}},
194 {DecLcStateNumRep{DecLcStTestUnlocked6}},
195 {DecLcStateNumRep{DecLcStTestLocked6}},
196 {DecLcStateNumRep{DecLcStTestUnlocked7}},
197 {DecLcStateNumRep{DecLcStDev}},
198 {DecLcStateNumRep{DecLcStProd}},
199 {DecLcStateNumRep{DecLcStProdEnd}},
200 {DecLcStateNumRep{DecLcStRma}},
201 1/1 {DecLcStateNumRep{DecLcStScrap}}: ;
Tests: T1 T2 T3
202 default: trans_invalid_error_o = 1'b1;
203 endcase // trans_target_i
204 end
MISSING_ELSE
Cond Coverage for Module :
lc_ctrl_state_transition
| Total | Covered | Percent |
|---|
| Conditions | 14 | 8 | 57.14 |
| Logical | 14 | 8 | 57.14 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
EXPRESSION
Number Term
1 (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) ||
2 (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Unreachable | |
| 0 | 1 | Unreachable | |
| 1 | 0 | Unreachable | |
LINE 66
SUB-EXPRESSION (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}})
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Unreachable | |
LINE 66
SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
----------------------------------------1---------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Unreachable | |
LINE 118
EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}})
------------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T13 |
LINE 133
EXPRESSION
Number Term
1 (dec_lc_state_i[0] <= DecLcStScrap) &&
2 (trans_target_i[0] <= DecLcStScrap) &&
3 (dec_lc_state_i[1] <= DecLcStScrap) &&
4 (trans_target_i[1] <= DecLcStScrap))
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION
Number Term
1 (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) ||
2 (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T22,T27 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 140
SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx)
---------------------------------------------1---------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T13,T22,T27 |
| 1 | Covered | T1,T2,T3 |
LINE 140
SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)
---------------------------------------------1---------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T13,T22,T27 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
lc_ctrl_state_transition
| Line No. | Total | Covered | Percent |
| Branches |
|
58 |
52 |
89.66 |
| IF |
63 |
2 |
1 |
50.00 |
| IF |
73 |
29 |
28 |
96.55 |
| IF |
125 |
27 |
23 |
85.19 |
63 if (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i && fsm_state_i == IdleSt)
-1-
64 begin
65 // We only allow transitions from RAW -> TEST_UNLOCKED0
66 if (dec_lc_state_i != {DecLcStateNumRep{DecLcStRaw}} ||
-2-
67 trans_target_i != {DecLcStateNumRep{DecLcStTestUnlocked0}}) begin
68 trans_invalid_error_o = 1'b1;
==> (Unreachable)
69 end
MISSING_ELSE
==>
70 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Unreachable |
|
| 1 |
0 |
Not Covered |
|
| 0 |
- |
Covered |
T1,T2,T3 |
73 if (fsm_state_i inside {CntIncrSt,
-1-
74 CntProgSt,
75 // Since OTP programming is incremental, we have to keep the next
76 // counter state assigned when performing the actual state transition
77 // in the second programming pass to prevent OTP programming errors.
78 TransCheckSt,
79 TokenCheck0St,
80 TokenCheck1St,
81 TransProgSt}) begin
82 // In this state, the life cycle counter is incremented.
83 // Throw an error if the counter is already maxed out.
84 unique case (lc_cnt_i)
-2-
85 LcCnt0: next_lc_cnt_o = LcCnt1;
==>
86 LcCnt1: next_lc_cnt_o = LcCnt2;
==>
87 LcCnt2: next_lc_cnt_o = LcCnt3;
==>
88 LcCnt3: next_lc_cnt_o = LcCnt4;
==>
89 LcCnt4: next_lc_cnt_o = LcCnt5;
==>
90 LcCnt5: next_lc_cnt_o = LcCnt6;
==>
91 LcCnt6: next_lc_cnt_o = LcCnt7;
==>
92 LcCnt7: next_lc_cnt_o = LcCnt8;
==>
93 LcCnt8: next_lc_cnt_o = LcCnt9;
==>
94 LcCnt9: next_lc_cnt_o = LcCnt10;
==>
95 LcCnt10: next_lc_cnt_o = LcCnt11;
==>
96 LcCnt11: next_lc_cnt_o = LcCnt12;
==>
97 LcCnt12: next_lc_cnt_o = LcCnt13;
==>
98 LcCnt13: next_lc_cnt_o = LcCnt14;
==>
99 LcCnt14: next_lc_cnt_o = LcCnt15;
==>
100 LcCnt15: next_lc_cnt_o = LcCnt16;
==>
101 LcCnt16: next_lc_cnt_o = LcCnt17;
==>
102 LcCnt17: next_lc_cnt_o = LcCnt18;
==>
103 LcCnt18: next_lc_cnt_o = LcCnt19;
==>
104 LcCnt19: next_lc_cnt_o = LcCnt20;
==>
105 LcCnt20: next_lc_cnt_o = LcCnt21;
==>
106 LcCnt21: next_lc_cnt_o = LcCnt22;
==>
107 LcCnt22: next_lc_cnt_o = LcCnt23;
==>
108 LcCnt23: next_lc_cnt_o = LcCnt24;
==>
109 LcCnt24: trans_cnt_oflw_error_o = 1'b1;
==>
110 default: trans_cnt_oflw_error_o = 1'b1;
==>
111 endcase // lc_cnt_i
112
113 // We always allow transitions into the SCRAP state, so the overflow error is silenced in that
114 // particular case. In that case we max out the transition counter and force the
115 // next_lc_state already into SCRAP so that the error silencing above cannot be abused. This
116 // means that when moving to SCRAP state, we program LcStScrap twice: once during the counter
117 // increment phase, and once during the actual state programming phase.
118 if (trans_target_i == {DecLcStateNumRep{DecLcStScrap}}) begin
-3-
119 next_lc_cnt_o = LcCnt24;
==>
120 next_lc_state_o = LcStScrap;
121 trans_cnt_oflw_error_o = 1'b0;
122 end
MISSING_ELSE
==>
123 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
LcCnt0 |
- |
Covered |
T17,T18,T19 |
| 1 |
LcCnt1 |
- |
Covered |
T1,T3,T13 |
| 1 |
LcCnt2 |
- |
Covered |
T1,T13,T14 |
| 1 |
LcCnt3 |
- |
Covered |
T1,T4,T13 |
| 1 |
LcCnt4 |
- |
Covered |
T4,T13,T14 |
| 1 |
LcCnt5 |
- |
Covered |
T3,T13,T14 |
| 1 |
LcCnt6 |
- |
Covered |
T3,T4,T13 |
| 1 |
LcCnt7 |
- |
Covered |
T1,T4,T13 |
| 1 |
LcCnt8 |
- |
Covered |
T1,T13,T14 |
| 1 |
LcCnt9 |
- |
Covered |
T1,T13,T14 |
| 1 |
LcCnt10 |
- |
Covered |
T1,T4,T13 |
| 1 |
LcCnt11 |
- |
Covered |
T4,T14,T16 |
| 1 |
LcCnt12 |
- |
Covered |
T3,T4,T13 |
| 1 |
LcCnt13 |
- |
Covered |
T3,T4,T13 |
| 1 |
LcCnt14 |
- |
Covered |
T13,T14,T16 |
| 1 |
LcCnt15 |
- |
Covered |
T13,T14,T16 |
| 1 |
LcCnt16 |
- |
Covered |
T14,T20,T21 |
| 1 |
LcCnt17 |
- |
Covered |
T4,T13,T14 |
| 1 |
LcCnt18 |
- |
Covered |
T13,T17,T20 |
| 1 |
LcCnt19 |
- |
Covered |
T13,T14,T6 |
| 1 |
LcCnt20 |
- |
Covered |
T1,T13,T14 |
| 1 |
LcCnt21 |
- |
Covered |
T13,T14,T6 |
| 1 |
LcCnt22 |
- |
Covered |
T1,T2,T4 |
| 1 |
LcCnt23 |
- |
Covered |
T13,T14,T16 |
| 1 |
LcCnt24 |
- |
Covered |
T13,T17,T22 |
| 1 |
default |
- |
Not Covered |
|
| 1 |
- |
1 |
Covered |
T1,T4,T13 |
| 1 |
- |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
Covered |
T1,T2,T3 |
125 if (fsm_state_i inside {TransCheckSt,
-1-
126 TokenCheck0St,
127 TokenCheck1St,
128 TransProgSt}) begin
129 // SEC_CM: STATE.CONFIG.SPARSE
130 // Check that the decoded transition indexes are valid before indexing the state transition
131 // matrix. We perform the check twice with different indices into the replicated state
132 // enumeration.
133 if (dec_lc_state_i[0] <= DecLcStScrap &&
-2-
134 trans_target_i[0] <= DecLcStScrap &&
135 dec_lc_state_i[1] <= DecLcStScrap &&
136 trans_target_i[1] <= DecLcStScrap) begin
137 // Check the state transition token matrix in order to see whether this transition is valid.
138 // All transitions have a token index value different from InvalidTokenIdx. We perform the
139 // check twice with different indices into the replicated state enumeration.
140 if (TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx ||
-3-
141 TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx) begin
142 // Encode the target state.
143 // Note that the life cycle encoding itself also ensures that only certain transitions are
144 // possible. So even if this logic here is tampered with, the encoding values won't allow
145 // an invalid transition (instead, the programming operation will fail and leave the life
146 // cycle state corrupted/invalid).
147 unique case (trans_target_i)
-4-
148 {DecLcStateNumRep{DecLcStRaw}}: next_lc_state_o = LcStRaw;
==>
149 {DecLcStateNumRep{DecLcStTestUnlocked0}}: next_lc_state_o = LcStTestUnlocked0;
==>
150 {DecLcStateNumRep{DecLcStTestLocked0}}: next_lc_state_o = LcStTestLocked0;
==>
151 {DecLcStateNumRep{DecLcStTestUnlocked1}}: next_lc_state_o = LcStTestUnlocked1;
==>
152 {DecLcStateNumRep{DecLcStTestLocked1}}: next_lc_state_o = LcStTestLocked1;
==>
153 {DecLcStateNumRep{DecLcStTestUnlocked2}}: next_lc_state_o = LcStTestUnlocked2;
==>
154 {DecLcStateNumRep{DecLcStTestLocked2}}: next_lc_state_o = LcStTestLocked2;
==>
155 {DecLcStateNumRep{DecLcStTestUnlocked3}}: next_lc_state_o = LcStTestUnlocked3;
==>
156 {DecLcStateNumRep{DecLcStTestLocked3}}: next_lc_state_o = LcStTestLocked3;
==>
157 {DecLcStateNumRep{DecLcStTestUnlocked4}}: next_lc_state_o = LcStTestUnlocked4;
==>
158 {DecLcStateNumRep{DecLcStTestLocked4}}: next_lc_state_o = LcStTestLocked4;
==>
159 {DecLcStateNumRep{DecLcStTestUnlocked5}}: next_lc_state_o = LcStTestUnlocked5;
==>
160 {DecLcStateNumRep{DecLcStTestLocked5}}: next_lc_state_o = LcStTestLocked5;
==>
161 {DecLcStateNumRep{DecLcStTestUnlocked6}}: next_lc_state_o = LcStTestUnlocked6;
==>
162 {DecLcStateNumRep{DecLcStTestLocked6}}: next_lc_state_o = LcStTestLocked6;
==>
163 {DecLcStateNumRep{DecLcStTestUnlocked7}}: next_lc_state_o = LcStTestUnlocked7;
==>
164 {DecLcStateNumRep{DecLcStDev}}: next_lc_state_o = LcStDev;
==>
165 {DecLcStateNumRep{DecLcStProd}}: next_lc_state_o = LcStProd;
==>
166 {DecLcStateNumRep{DecLcStProdEnd}}: next_lc_state_o = LcStProdEnd;
==>
167 {DecLcStateNumRep{DecLcStRma}}: next_lc_state_o = LcStRma;
==>
168 {DecLcStateNumRep{DecLcStScrap}}: next_lc_state_o = LcStScrap;
==>
169 default: trans_invalid_error_o = 1'b1;
==>
170 endcase // trans_target_i
171 end else begin
172 trans_invalid_error_o = 1'b1;
==>
173 end
174 end else begin
175 trans_invalid_error_o = 1'b1;
==>
176 end
177
178 // SEC_CM: STATE.CONFIG.SPARSE
179 // Check that the internally re-encoded life cycle state has a correct encoding.
180 unique case (dec_lc_state_i)
-5-
181 {DecLcStateNumRep{DecLcStRaw}},
182 {DecLcStateNumRep{DecLcStTestUnlocked0}},
183 {DecLcStateNumRep{DecLcStTestLocked0}},
184 {DecLcStateNumRep{DecLcStTestUnlocked1}},
185 {DecLcStateNumRep{DecLcStTestLocked1}},
186 {DecLcStateNumRep{DecLcStTestUnlocked2}},
187 {DecLcStateNumRep{DecLcStTestLocked2}},
188 {DecLcStateNumRep{DecLcStTestUnlocked3}},
189 {DecLcStateNumRep{DecLcStTestLocked3}},
190 {DecLcStateNumRep{DecLcStTestUnlocked4}},
191 {DecLcStateNumRep{DecLcStTestLocked4}},
192 {DecLcStateNumRep{DecLcStTestUnlocked5}},
193 {DecLcStateNumRep{DecLcStTestLocked5}},
194 {DecLcStateNumRep{DecLcStTestUnlocked6}},
195 {DecLcStateNumRep{DecLcStTestLocked6}},
196 {DecLcStateNumRep{DecLcStTestUnlocked7}},
197 {DecLcStateNumRep{DecLcStDev}},
198 {DecLcStateNumRep{DecLcStProd}},
199 {DecLcStateNumRep{DecLcStProdEnd}},
200 {DecLcStateNumRep{DecLcStRma}},
201 {DecLcStateNumRep{DecLcStScrap}}: ;
==>
202 default: trans_invalid_error_o = 1'b1;
==>
203 endcase // trans_target_i
204 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} |
- |
Not Covered |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} |
- |
Covered |
T2,T23,T24 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} |
- |
Covered |
T14,T21,T25 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} |
- |
Covered |
T20,T22,T24 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} |
- |
Covered |
T1,T13,T20 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} |
- |
Covered |
T3,T13,T20 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} |
- |
Covered |
T1,T13,T14 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} |
- |
Covered |
T14,T24,T26 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} |
- |
Covered |
T1,T13,T17 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} |
- |
Covered |
T14,T16,T20 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} |
- |
Covered |
T13,T5,T20 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} |
- |
Covered |
T13,T14,T16 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} |
- |
Covered |
T5,T20,T21 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} |
- |
Covered |
T3,T14,T17 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} |
- |
Covered |
T13,T20,T21 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} |
- |
Covered |
T16,T17,T20 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} |
- |
Covered |
T3,T13,T14 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} |
- |
Covered |
T1,T3,T13 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} |
- |
Covered |
T13,T14,T16 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} |
- |
Covered |
T1,T13,T14 |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}} |
- |
Covered |
T1,T13,T14 |
| 1 |
1 |
1 |
default |
- |
Not Covered |
|
| 1 |
1 |
0 |
- |
- |
Covered |
T13,T22,T27 |
| 1 |
0 |
- |
- |
- |
Not Covered |
|
| 1 |
- |
- |
- |
CASEITEM-1: {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}} |
Covered |
T1,T2,T3 |
| 1 |
- |
- |
- |
default |
Not Covered |
|
| 0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 65 | 64 | 98.46 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| ALWAYS | 52 | 64 | 63 | 98.44 |
44 logic unused_trans_cmd;
45 1/1 assign unused_trans_cmd = trans_cmd_i;
Tests: T1 T2 T3
46 end
47
48 // The decoder logic below checks whether a given transition edge
49 // is valid and computes the next lc counter ans state vectors.
50 always_comb begin : p_lc_state_transition
51 // Decoded state defaults
52 1/1 next_lc_cnt_o = lc_cnt_i;
Tests: T1 T2 T3
53 1/1 next_lc_state_o = lc_state_i;
Tests: T1 T2 T3
54 1/1 trans_cnt_oflw_error_o = 1'b0;
Tests: T1 T2 T3
55 1/1 trans_invalid_error_o = 1'b0;
Tests: T1 T2 T3
56
57 // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
58 // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
59 // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
60 // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
61 // ---------------------------------------------------------------
62 // Only enter here if volatile RAW unlock is available and enabled.
63 1/1 if (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i && fsm_state_i == IdleSt)
Tests: T1 T2 T3
64 begin
65 // We only allow transitions from RAW -> TEST_UNLOCKED0
66 unreachable if (dec_lc_state_i != {DecLcStateNumRep{DecLcStRaw}} ||
67 trans_target_i != {DecLcStateNumRep{DecLcStTestUnlocked0}}) begin
68 unreachable trans_invalid_error_o = 1'b1;
69 end
==> MISSING_ELSE
70 end
MISSING_ELSE
71 // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
72
73 1/1 if (fsm_state_i inside {CntIncrSt,
Tests: T1 T2 T3
74 CntProgSt,
75 // Since OTP programming is incremental, we have to keep the next
76 // counter state assigned when performing the actual state transition
77 // in the second programming pass to prevent OTP programming errors.
78 TransCheckSt,
79 TokenCheck0St,
80 TokenCheck1St,
81 TransProgSt}) begin
82 // In this state, the life cycle counter is incremented.
83 // Throw an error if the counter is already maxed out.
84 1/1 unique case (lc_cnt_i)
Tests: T1 T2 T3
85 1/1 LcCnt0: next_lc_cnt_o = LcCnt1;
Tests: T17 T18 T19
86 1/1 LcCnt1: next_lc_cnt_o = LcCnt2;
Tests: T1 T3 T13
87 1/1 LcCnt2: next_lc_cnt_o = LcCnt3;
Tests: T1 T13 T14
88 1/1 LcCnt3: next_lc_cnt_o = LcCnt4;
Tests: T1 T4 T13
89 1/1 LcCnt4: next_lc_cnt_o = LcCnt5;
Tests: T4 T13 T14
90 1/1 LcCnt5: next_lc_cnt_o = LcCnt6;
Tests: T3 T13 T14
91 1/1 LcCnt6: next_lc_cnt_o = LcCnt7;
Tests: T3 T4 T13
92 1/1 LcCnt7: next_lc_cnt_o = LcCnt8;
Tests: T1 T4 T13
93 1/1 LcCnt8: next_lc_cnt_o = LcCnt9;
Tests: T1 T13 T14
94 1/1 LcCnt9: next_lc_cnt_o = LcCnt10;
Tests: T1 T13 T14
95 1/1 LcCnt10: next_lc_cnt_o = LcCnt11;
Tests: T1 T4 T13
96 1/1 LcCnt11: next_lc_cnt_o = LcCnt12;
Tests: T4 T14 T16
97 1/1 LcCnt12: next_lc_cnt_o = LcCnt13;
Tests: T3 T4 T13
98 1/1 LcCnt13: next_lc_cnt_o = LcCnt14;
Tests: T3 T4 T13
99 1/1 LcCnt14: next_lc_cnt_o = LcCnt15;
Tests: T13 T14 T16
100 1/1 LcCnt15: next_lc_cnt_o = LcCnt16;
Tests: T13 T14 T16
101 1/1 LcCnt16: next_lc_cnt_o = LcCnt17;
Tests: T14 T20 T21
102 1/1 LcCnt17: next_lc_cnt_o = LcCnt18;
Tests: T4 T13 T14
103 1/1 LcCnt18: next_lc_cnt_o = LcCnt19;
Tests: T13 T17 T20
104 1/1 LcCnt19: next_lc_cnt_o = LcCnt20;
Tests: T13 T14 T6
105 1/1 LcCnt20: next_lc_cnt_o = LcCnt21;
Tests: T1 T13 T14
106 1/1 LcCnt21: next_lc_cnt_o = LcCnt22;
Tests: T13 T14 T6
107 1/1 LcCnt22: next_lc_cnt_o = LcCnt23;
Tests: T1 T2 T4
108 1/1 LcCnt23: next_lc_cnt_o = LcCnt24;
Tests: T13 T14 T16
109 1/1 LcCnt24: trans_cnt_oflw_error_o = 1'b1;
Tests: T13 T17 T22
110 default: trans_cnt_oflw_error_o = 1'b1;
Exclude Annotation: VC_COV_UNR
111 endcase // lc_cnt_i
112
113 // We always allow transitions into the SCRAP state, so the overflow error is silenced in that
114 // particular case. In that case we max out the transition counter and force the
115 // next_lc_state already into SCRAP so that the error silencing above cannot be abused. This
116 // means that when moving to SCRAP state, we program LcStScrap twice: once during the counter
117 // increment phase, and once during the actual state programming phase.
118 1/1 if (trans_target_i == {DecLcStateNumRep{DecLcStScrap}}) begin
Tests: T1 T2 T3
119 1/1 next_lc_cnt_o = LcCnt24;
Tests: T1 T4 T13
120 1/1 next_lc_state_o = LcStScrap;
Tests: T1 T4 T13
121 1/1 trans_cnt_oflw_error_o = 1'b0;
Tests: T1 T4 T13
122 end
MISSING_ELSE
123 end
MISSING_ELSE
124
125 1/1 if (fsm_state_i inside {TransCheckSt,
Tests: T1 T2 T3
126 TokenCheck0St,
127 TokenCheck1St,
128 TransProgSt}) begin
129 // SEC_CM: STATE.CONFIG.SPARSE
130 // Check that the decoded transition indexes are valid before indexing the state transition
131 // matrix. We perform the check twice with different indices into the replicated state
132 // enumeration.
133 1/1 if (dec_lc_state_i[0] <= DecLcStScrap &&
Tests: T1 T2 T3
134 trans_target_i[0] <= DecLcStScrap &&
135 dec_lc_state_i[1] <= DecLcStScrap &&
136 trans_target_i[1] <= DecLcStScrap) begin
137 // Check the state transition token matrix in order to see whether this transition is valid.
138 // All transitions have a token index value different from InvalidTokenIdx. We perform the
139 // check twice with different indices into the replicated state enumeration.
140 1/1 if (TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx ||
Tests: T1 T2 T3
141 TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx) begin
142 // Encode the target state.
143 // Note that the life cycle encoding itself also ensures that only certain transitions are
144 // possible. So even if this logic here is tampered with, the encoding values won't allow
145 // an invalid transition (instead, the programming operation will fail and leave the life
146 // cycle state corrupted/invalid).
147 1/1 unique case (trans_target_i)
Tests: T1 T2 T3
148 excluded {DecLcStateNumRep{DecLcStRaw}}: next_lc_state_o = LcStRaw;
Exclude Annotation: VC_COV_UNR
149 1/1 {DecLcStateNumRep{DecLcStTestUnlocked0}}: next_lc_state_o = LcStTestUnlocked0;
Tests: T2 T23 T24
150 1/1 {DecLcStateNumRep{DecLcStTestLocked0}}: next_lc_state_o = LcStTestLocked0;
Tests: T14 T21 T25
151 1/1 {DecLcStateNumRep{DecLcStTestUnlocked1}}: next_lc_state_o = LcStTestUnlocked1;
Tests: T20 T22 T24
152 1/1 {DecLcStateNumRep{DecLcStTestLocked1}}: next_lc_state_o = LcStTestLocked1;
Tests: T1 T13 T20
153 1/1 {DecLcStateNumRep{DecLcStTestUnlocked2}}: next_lc_state_o = LcStTestUnlocked2;
Tests: T3 T13 T20
154 1/1 {DecLcStateNumRep{DecLcStTestLocked2}}: next_lc_state_o = LcStTestLocked2;
Tests: T1 T13 T14
155 1/1 {DecLcStateNumRep{DecLcStTestUnlocked3}}: next_lc_state_o = LcStTestUnlocked3;
Tests: T14 T24 T26
156 1/1 {DecLcStateNumRep{DecLcStTestLocked3}}: next_lc_state_o = LcStTestLocked3;
Tests: T1 T13 T17
157 1/1 {DecLcStateNumRep{DecLcStTestUnlocked4}}: next_lc_state_o = LcStTestUnlocked4;
Tests: T14 T16 T20
158 1/1 {DecLcStateNumRep{DecLcStTestLocked4}}: next_lc_state_o = LcStTestLocked4;
Tests: T13 T5 T20
159 1/1 {DecLcStateNumRep{DecLcStTestUnlocked5}}: next_lc_state_o = LcStTestUnlocked5;
Tests: T13 T14 T16
160 1/1 {DecLcStateNumRep{DecLcStTestLocked5}}: next_lc_state_o = LcStTestLocked5;
Tests: T5 T20 T21
161 1/1 {DecLcStateNumRep{DecLcStTestUnlocked6}}: next_lc_state_o = LcStTestUnlocked6;
Tests: T3 T14 T17
162 1/1 {DecLcStateNumRep{DecLcStTestLocked6}}: next_lc_state_o = LcStTestLocked6;
Tests: T13 T20 T21
163 1/1 {DecLcStateNumRep{DecLcStTestUnlocked7}}: next_lc_state_o = LcStTestUnlocked7;
Tests: T16 T17 T20
164 1/1 {DecLcStateNumRep{DecLcStDev}}: next_lc_state_o = LcStDev;
Tests: T3 T13 T14
165 1/1 {DecLcStateNumRep{DecLcStProd}}: next_lc_state_o = LcStProd;
Tests: T1 T3 T13
166 1/1 {DecLcStateNumRep{DecLcStProdEnd}}: next_lc_state_o = LcStProdEnd;
Tests: T13 T14 T16
167 1/1 {DecLcStateNumRep{DecLcStRma}}: next_lc_state_o = LcStRma;
Tests: T1 T13 T14
168 1/1 {DecLcStateNumRep{DecLcStScrap}}: next_lc_state_o = LcStScrap;
Tests: T1 T13 T14
169 default: trans_invalid_error_o = 1'b1;
170 endcase // trans_target_i
171 end else begin
172 1/1 trans_invalid_error_o = 1'b1;
Tests: T13 T22 T27
173 end
174 end else begin
175 0/1 ==> trans_invalid_error_o = 1'b1;
176 end
177
178 // SEC_CM: STATE.CONFIG.SPARSE
179 // Check that the internally re-encoded life cycle state has a correct encoding.
180 1/1 unique case (dec_lc_state_i)
Tests: T1 T2 T3
181 {DecLcStateNumRep{DecLcStRaw}},
182 {DecLcStateNumRep{DecLcStTestUnlocked0}},
183 {DecLcStateNumRep{DecLcStTestLocked0}},
184 {DecLcStateNumRep{DecLcStTestUnlocked1}},
185 {DecLcStateNumRep{DecLcStTestLocked1}},
186 {DecLcStateNumRep{DecLcStTestUnlocked2}},
187 {DecLcStateNumRep{DecLcStTestLocked2}},
188 {DecLcStateNumRep{DecLcStTestUnlocked3}},
189 {DecLcStateNumRep{DecLcStTestLocked3}},
190 {DecLcStateNumRep{DecLcStTestUnlocked4}},
191 {DecLcStateNumRep{DecLcStTestLocked4}},
192 {DecLcStateNumRep{DecLcStTestUnlocked5}},
193 {DecLcStateNumRep{DecLcStTestLocked5}},
194 {DecLcStateNumRep{DecLcStTestUnlocked6}},
195 {DecLcStateNumRep{DecLcStTestLocked6}},
196 {DecLcStateNumRep{DecLcStTestUnlocked7}},
197 {DecLcStateNumRep{DecLcStDev}},
198 {DecLcStateNumRep{DecLcStProd}},
199 {DecLcStateNumRep{DecLcStProdEnd}},
200 {DecLcStateNumRep{DecLcStRma}},
201 1/1 {DecLcStateNumRep{DecLcStScrap}}: ;
Tests: T1 T2 T3
202 default: trans_invalid_error_o = 1'b1;
Exclude Annotation: VC_COV_UNR
203 endcase // trans_target_i
204 end
MISSING_ELSE
Cond Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition
| Total | Covered | Percent |
|---|
| Conditions | 12 | 8 | 66.67 |
| Logical | 12 | 8 | 66.67 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
EXPRESSION
Number Term
1 (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) ||
2 (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Unreachable | |
| 0 | 1 | Unreachable | |
| 1 | 0 | Unreachable | |
LINE 66
SUB-EXPRESSION (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}})
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Unreachable | |
LINE 66
SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
----------------------------------------1---------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Unreachable | |
LINE 118
EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}})
------------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T13 |
LINE 133
EXPRESSION
Number Term
1 (dec_lc_state_i[0] <= DecLcStScrap) &&
2 (trans_target_i[0] <= DecLcStScrap) &&
3 (dec_lc_state_i[1] <= DecLcStScrap) &&
4 (trans_target_i[1] <= DecLcStScrap))
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION
Number Term
1 (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) ||
2 (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx))
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T13,T22,T27 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 140
SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx)
---------------------------------------------1---------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T13,T22,T27 |
| 1 | Covered | T1,T2,T3 |
LINE 140
SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)
---------------------------------------------1---------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T13,T22,T27 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition
| Line No. | Total | Covered | Percent |
| Branches |
|
54 |
52 |
96.30 |
| IF |
63 |
1 |
1 |
100.00 |
| IF |
73 |
28 |
28 |
100.00 |
| IF |
125 |
25 |
23 |
92.00 |
63 if (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i && fsm_state_i == IdleSt)
-1-
64 begin
65 // We only allow transitions from RAW -> TEST_UNLOCKED0
66 if (dec_lc_state_i != {DecLcStateNumRep{DecLcStRaw}} ||
-2-
67 trans_target_i != {DecLcStateNumRep{DecLcStTestUnlocked0}}) begin
68 trans_invalid_error_o = 1'b1;
==> (Unreachable)
69 end
MISSING_ELSE
==> (Excluded)
Exclude Annotation: VC_COV_UNR
70 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
1 |
Unreachable |
|
|
| 1 |
0 |
Excluded |
|
VC_COV_UNR |
| 0 |
- |
Covered |
T1,T2,T3 |
|
73 if (fsm_state_i inside {CntIncrSt,
-1-
74 CntProgSt,
75 // Since OTP programming is incremental, we have to keep the next
76 // counter state assigned when performing the actual state transition
77 // in the second programming pass to prevent OTP programming errors.
78 TransCheckSt,
79 TokenCheck0St,
80 TokenCheck1St,
81 TransProgSt}) begin
82 // In this state, the life cycle counter is incremented.
83 // Throw an error if the counter is already maxed out.
84 unique case (lc_cnt_i)
-2-
85 LcCnt0: next_lc_cnt_o = LcCnt1;
==>
86 LcCnt1: next_lc_cnt_o = LcCnt2;
==>
87 LcCnt2: next_lc_cnt_o = LcCnt3;
==>
88 LcCnt3: next_lc_cnt_o = LcCnt4;
==>
89 LcCnt4: next_lc_cnt_o = LcCnt5;
==>
90 LcCnt5: next_lc_cnt_o = LcCnt6;
==>
91 LcCnt6: next_lc_cnt_o = LcCnt7;
==>
92 LcCnt7: next_lc_cnt_o = LcCnt8;
==>
93 LcCnt8: next_lc_cnt_o = LcCnt9;
==>
94 LcCnt9: next_lc_cnt_o = LcCnt10;
==>
95 LcCnt10: next_lc_cnt_o = LcCnt11;
==>
96 LcCnt11: next_lc_cnt_o = LcCnt12;
==>
97 LcCnt12: next_lc_cnt_o = LcCnt13;
==>
98 LcCnt13: next_lc_cnt_o = LcCnt14;
==>
99 LcCnt14: next_lc_cnt_o = LcCnt15;
==>
100 LcCnt15: next_lc_cnt_o = LcCnt16;
==>
101 LcCnt16: next_lc_cnt_o = LcCnt17;
==>
102 LcCnt17: next_lc_cnt_o = LcCnt18;
==>
103 LcCnt18: next_lc_cnt_o = LcCnt19;
==>
104 LcCnt19: next_lc_cnt_o = LcCnt20;
==>
105 LcCnt20: next_lc_cnt_o = LcCnt21;
==>
106 LcCnt21: next_lc_cnt_o = LcCnt22;
==>
107 LcCnt22: next_lc_cnt_o = LcCnt23;
==>
108 LcCnt23: next_lc_cnt_o = LcCnt24;
==>
109 LcCnt24: trans_cnt_oflw_error_o = 1'b1;
==>
110 default: trans_cnt_oflw_error_o = 1'b1;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
111 endcase // lc_cnt_i
112
113 // We always allow transitions into the SCRAP state, so the overflow error is silenced in that
114 // particular case. In that case we max out the transition counter and force the
115 // next_lc_state already into SCRAP so that the error silencing above cannot be abused. This
116 // means that when moving to SCRAP state, we program LcStScrap twice: once during the counter
117 // increment phase, and once during the actual state programming phase.
118 if (trans_target_i == {DecLcStateNumRep{DecLcStScrap}}) begin
-3-
119 next_lc_cnt_o = LcCnt24;
==>
120 next_lc_state_o = LcStScrap;
121 trans_cnt_oflw_error_o = 1'b0;
122 end
MISSING_ELSE
==>
123 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
| 1 |
LcCnt0 |
- |
Covered |
T17,T18,T19 |
|
| 1 |
LcCnt1 |
- |
Covered |
T1,T3,T13 |
|
| 1 |
LcCnt2 |
- |
Covered |
T1,T13,T14 |
|
| 1 |
LcCnt3 |
- |
Covered |
T1,T4,T13 |
|
| 1 |
LcCnt4 |
- |
Covered |
T4,T13,T14 |
|
| 1 |
LcCnt5 |
- |
Covered |
T3,T13,T14 |
|
| 1 |
LcCnt6 |
- |
Covered |
T3,T4,T13 |
|
| 1 |
LcCnt7 |
- |
Covered |
T1,T4,T13 |
|
| 1 |
LcCnt8 |
- |
Covered |
T1,T13,T14 |
|
| 1 |
LcCnt9 |
- |
Covered |
T1,T13,T14 |
|
| 1 |
LcCnt10 |
- |
Covered |
T1,T4,T13 |
|
| 1 |
LcCnt11 |
- |
Covered |
T4,T14,T16 |
|
| 1 |
LcCnt12 |
- |
Covered |
T3,T4,T13 |
|
| 1 |
LcCnt13 |
- |
Covered |
T3,T4,T13 |
|
| 1 |
LcCnt14 |
- |
Covered |
T13,T14,T16 |
|
| 1 |
LcCnt15 |
- |
Covered |
T13,T14,T16 |
|
| 1 |
LcCnt16 |
- |
Covered |
T14,T20,T21 |
|
| 1 |
LcCnt17 |
- |
Covered |
T4,T13,T14 |
|
| 1 |
LcCnt18 |
- |
Covered |
T13,T17,T20 |
|
| 1 |
LcCnt19 |
- |
Covered |
T13,T14,T6 |
|
| 1 |
LcCnt20 |
- |
Covered |
T1,T13,T14 |
|
| 1 |
LcCnt21 |
- |
Covered |
T13,T14,T6 |
|
| 1 |
LcCnt22 |
- |
Covered |
T1,T2,T4 |
|
| 1 |
LcCnt23 |
- |
Covered |
T13,T14,T16 |
|
| 1 |
LcCnt24 |
- |
Covered |
T13,T17,T22 |
|
| 1 |
default |
- |
Excluded |
|
VC_COV_UNR |
| 1 |
- |
1 |
Covered |
T1,T4,T13 |
|
| 1 |
- |
0 |
Covered |
T1,T2,T3 |
|
| 0 |
- |
- |
Covered |
T1,T2,T3 |
|
125 if (fsm_state_i inside {TransCheckSt,
-1-
126 TokenCheck0St,
127 TokenCheck1St,
128 TransProgSt}) begin
129 // SEC_CM: STATE.CONFIG.SPARSE
130 // Check that the decoded transition indexes are valid before indexing the state transition
131 // matrix. We perform the check twice with different indices into the replicated state
132 // enumeration.
133 if (dec_lc_state_i[0] <= DecLcStScrap &&
-2-
134 trans_target_i[0] <= DecLcStScrap &&
135 dec_lc_state_i[1] <= DecLcStScrap &&
136 trans_target_i[1] <= DecLcStScrap) begin
137 // Check the state transition token matrix in order to see whether this transition is valid.
138 // All transitions have a token index value different from InvalidTokenIdx. We perform the
139 // check twice with different indices into the replicated state enumeration.
140 if (TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx ||
-3-
141 TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx) begin
142 // Encode the target state.
143 // Note that the life cycle encoding itself also ensures that only certain transitions are
144 // possible. So even if this logic here is tampered with, the encoding values won't allow
145 // an invalid transition (instead, the programming operation will fail and leave the life
146 // cycle state corrupted/invalid).
147 unique case (trans_target_i)
-4-
148 {DecLcStateNumRep{DecLcStRaw}}: next_lc_state_o = LcStRaw;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
149 {DecLcStateNumRep{DecLcStTestUnlocked0}}: next_lc_state_o = LcStTestUnlocked0;
==>
150 {DecLcStateNumRep{DecLcStTestLocked0}}: next_lc_state_o = LcStTestLocked0;
==>
151 {DecLcStateNumRep{DecLcStTestUnlocked1}}: next_lc_state_o = LcStTestUnlocked1;
==>
152 {DecLcStateNumRep{DecLcStTestLocked1}}: next_lc_state_o = LcStTestLocked1;
==>
153 {DecLcStateNumRep{DecLcStTestUnlocked2}}: next_lc_state_o = LcStTestUnlocked2;
==>
154 {DecLcStateNumRep{DecLcStTestLocked2}}: next_lc_state_o = LcStTestLocked2;
==>
155 {DecLcStateNumRep{DecLcStTestUnlocked3}}: next_lc_state_o = LcStTestUnlocked3;
==>
156 {DecLcStateNumRep{DecLcStTestLocked3}}: next_lc_state_o = LcStTestLocked3;
==>
157 {DecLcStateNumRep{DecLcStTestUnlocked4}}: next_lc_state_o = LcStTestUnlocked4;
==>
158 {DecLcStateNumRep{DecLcStTestLocked4}}: next_lc_state_o = LcStTestLocked4;
==>
159 {DecLcStateNumRep{DecLcStTestUnlocked5}}: next_lc_state_o = LcStTestUnlocked5;
==>
160 {DecLcStateNumRep{DecLcStTestLocked5}}: next_lc_state_o = LcStTestLocked5;
==>
161 {DecLcStateNumRep{DecLcStTestUnlocked6}}: next_lc_state_o = LcStTestUnlocked6;
==>
162 {DecLcStateNumRep{DecLcStTestLocked6}}: next_lc_state_o = LcStTestLocked6;
==>
163 {DecLcStateNumRep{DecLcStTestUnlocked7}}: next_lc_state_o = LcStTestUnlocked7;
==>
164 {DecLcStateNumRep{DecLcStDev}}: next_lc_state_o = LcStDev;
==>
165 {DecLcStateNumRep{DecLcStProd}}: next_lc_state_o = LcStProd;
==>
166 {DecLcStateNumRep{DecLcStProdEnd}}: next_lc_state_o = LcStProdEnd;
==>
167 {DecLcStateNumRep{DecLcStRma}}: next_lc_state_o = LcStRma;
==>
168 {DecLcStateNumRep{DecLcStScrap}}: next_lc_state_o = LcStScrap;
==>
169 default: trans_invalid_error_o = 1'b1;
==>
170 endcase // trans_target_i
171 end else begin
172 trans_invalid_error_o = 1'b1;
==>
173 end
174 end else begin
175 trans_invalid_error_o = 1'b1;
==>
176 end
177
178 // SEC_CM: STATE.CONFIG.SPARSE
179 // Check that the internally re-encoded life cycle state has a correct encoding.
180 unique case (dec_lc_state_i)
-5-
181 {DecLcStateNumRep{DecLcStRaw}},
182 {DecLcStateNumRep{DecLcStTestUnlocked0}},
183 {DecLcStateNumRep{DecLcStTestLocked0}},
184 {DecLcStateNumRep{DecLcStTestUnlocked1}},
185 {DecLcStateNumRep{DecLcStTestLocked1}},
186 {DecLcStateNumRep{DecLcStTestUnlocked2}},
187 {DecLcStateNumRep{DecLcStTestLocked2}},
188 {DecLcStateNumRep{DecLcStTestUnlocked3}},
189 {DecLcStateNumRep{DecLcStTestLocked3}},
190 {DecLcStateNumRep{DecLcStTestUnlocked4}},
191 {DecLcStateNumRep{DecLcStTestLocked4}},
192 {DecLcStateNumRep{DecLcStTestUnlocked5}},
193 {DecLcStateNumRep{DecLcStTestLocked5}},
194 {DecLcStateNumRep{DecLcStTestUnlocked6}},
195 {DecLcStateNumRep{DecLcStTestLocked6}},
196 {DecLcStateNumRep{DecLcStTestUnlocked7}},
197 {DecLcStateNumRep{DecLcStDev}},
198 {DecLcStateNumRep{DecLcStProd}},
199 {DecLcStateNumRep{DecLcStProdEnd}},
200 {DecLcStateNumRep{DecLcStRma}},
201 {DecLcStateNumRep{DecLcStScrap}}: ;
==>
202 default: trans_invalid_error_o = 1'b1;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
203 endcase // trans_target_i
204 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | Status | Tests | Exclude Annotation |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} |
- |
Excluded |
|
VC_COV_UNR |
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} |
- |
Covered |
T2,T23,T24 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} |
- |
Covered |
T14,T21,T25 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} |
- |
Covered |
T20,T22,T24 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} |
- |
Covered |
T1,T13,T20 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} |
- |
Covered |
T3,T13,T20 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} |
- |
Covered |
T1,T13,T14 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} |
- |
Covered |
T14,T24,T26 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} |
- |
Covered |
T1,T13,T17 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} |
- |
Covered |
T14,T16,T20 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} |
- |
Covered |
T13,T5,T20 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} |
- |
Covered |
T13,T14,T16 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} |
- |
Covered |
T5,T20,T21 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} |
- |
Covered |
T3,T14,T17 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} |
- |
Covered |
T13,T20,T21 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} |
- |
Covered |
T16,T17,T20 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} |
- |
Covered |
T3,T13,T14 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} |
- |
Covered |
T1,T3,T13 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} |
- |
Covered |
T13,T14,T16 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} |
- |
Covered |
T1,T13,T14 |
|
| 1 |
1 |
1 |
{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}} |
- |
Covered |
T1,T13,T14 |
|
| 1 |
1 |
1 |
default |
- |
Not Covered |
|
|
| 1 |
1 |
0 |
- |
- |
Covered |
T13,T22,T27 |
|
| 1 |
0 |
- |
- |
- |
Not Covered |
|
|
| 1 |
- |
- |
- |
CASEITEM-1: {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}} |
Covered |
T1,T2,T3 |
|
| 1 |
- |
- |
- |
default |
Excluded |
|
VC_COV_UNR |
| 0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|