Module Definition
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Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Toggle Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
clk1_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
sel_i No No No INPUT
clk_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT


Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 46944482 46942856 0 0
selKnown1 62075722 62074096 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 46944482 46942856 0 0
T1 12 11 0 0
T2 1 0 0 0
T3 11 10 0 0
T4 15 14 0 0
T5 26778 26776 0 0
T6 61631 61643 0 0
T7 43705 43718 0 0
T8 23567 23566 0 0
T12 65 64 0 0
T13 87 86 0 0
T14 74 73 0 0
T15 1 0 0 0
T16 8 7 0 0
T17 138725 138724 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 0 319396 0 0
T23 1 0 0 0
T28 59805 59804 0 0
T29 0 239204 0 0
T30 0 53399 0 0
T31 0 30179 0 0
T32 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 62075722 62074096 0 0
T1 9115 9114 0 0
T2 1392 1391 0 0
T3 6624 6623 0 0
T4 7239 7238 0 0
T5 19312 19311 0 0
T8 2 1 0 0
T9 0 3 0 0
T11 0 3 0 0
T12 21954 21953 0 0
T13 26665 26664 0 0
T14 36968 36967 0 0
T15 881 880 0 0
T16 32649 32648 0 0
T17 1 0 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 1 0 0 0
T23 1 0 0 0
T24 1 0 0 0
T28 1 0 0 0
T32 1 0 0 0
T33 0 3 0 0
T34 0 1 0 0
T35 0 1 0 0
T36 0 2 0 0
T37 0 3 0 0
T38 0 5 0 0
T39 0 5 0 0
T40 1 0 0 0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
clk1_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
sel_i No No No INPUT
clk_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
clk1_i Yes Yes T8,T9,T10 Yes T8,T9,T11 INPUT
sel_i No No No INPUT
clk_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T7
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 46900159 46899346 0 0
selKnown1 62074780 62073967 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 46900159 46899346 0 0
T5 26767 26766 0 0
T6 61631 61630 0 0
T7 43705 43704 0 0
T8 23567 23566 0 0
T17 138725 138724 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 0 319396 0 0
T23 1 0 0 0
T28 59805 59804 0 0
T29 0 239204 0 0
T30 0 53399 0 0
T31 0 30179 0 0
T32 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 62074780 62073967 0 0
T1 9115 9114 0 0
T2 1392 1391 0 0
T3 6624 6623 0 0
T4 7239 7238 0 0
T5 19312 19311 0 0
T12 21954 21953 0 0
T13 26665 26664 0 0
T14 36968 36967 0 0
T15 881 880 0 0
T16 32649 32648 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 44323 43510 0 0
selKnown1 942 129 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 44323 43510 0 0
T1 12 11 0 0
T2 1 0 0 0
T3 11 10 0 0
T4 15 14 0 0
T5 11 10 0 0
T6 0 13 0 0
T7 0 14 0 0
T12 65 64 0 0
T13 87 86 0 0
T14 74 73 0 0
T15 1 0 0 0
T16 8 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 942 129 0 0
T8 2 1 0 0
T9 0 3 0 0
T11 0 3 0 0
T17 1 0 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 1 0 0 0
T23 1 0 0 0
T24 1 0 0 0
T28 1 0 0 0
T32 1 0 0 0
T33 0 3 0 0
T34 0 1 0 0
T35 0 1 0 0
T36 0 2 0 0
T37 0 3 0 0
T38 0 5 0 0
T39 0 5 0 0
T40 1 0 0 0

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