Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.64	100.00	55.56	75.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	75.00			75.00
tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	75.00			75.00
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.00			75.00				gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.00			75.00				u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
clk1_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	86033203	86031565	0	0
selKnown1	115262271	115260633	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	86033203	86031565	0	0
T2	8	7	0	0
T3	8	7	0	0
T4	14	13	0	0
T5	7126	7124	0	0
T6	9708	9708	0	0
T7	40173	40172	0	0
T8	0	49590	0	0
T9	0	49427	0	0
T11	31292	31291	0	0
T12	55	54	0	0
T13	1	0	0	0
T14	1	0	0	0
T15	3	2	0	0
T16	1	0	0	0
T17	1	0	0	0
T21	1	80	0	0
T22	1	18	0	0
T24	1	4	0	0
T25	1	0	0	0
T31	1	0	0	0
T32	0	38141	0	0
T34	0	32795	0	0
T35	0	56795	0	0
T36	0	43939	0	0
T37	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	115262271	115260633	0	0
T1	1244	1243	0	0
T2	3619	3618	0	0
T3	4641	4640	0	0
T4	8343	8342	0	0
T8	4	3	0	0
T9	4	3	0	0
T10	0	7	0	0
T12	22135	22134	0	0
T13	771	770	0	0
T14	2640	2639	0	0
T15	1396	1395	0	0
T16	1379	1378	0	0
T17	610	609	0	0
T23	1	0	0	0
T27	1	0	0	0
T28	1	0	0	0
T29	1	0	0	0
T36	1	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	4	0	0
T41	0	3	0	0
T42	0	6	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	1	0	0	0
T46	1	0	0	0
T47	1	0	0	0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
clk1_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T5,T6,T11	Yes	T5,T6,T7	INPUT
clk1_i	Yes	Yes	T7,T8,T9	Yes	T8,T9,T10	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T5,T6,T11	Yes	T5,T6,T7	OUTPUT

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	85972292	85971473	0	0
selKnown1	115261329	115260510	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	85972292	85971473	0	0
T5	7124	7123	0	0
T6	9708	9707	0	0
T7	40173	40172	0	0
T8	0	49590	0	0
T9	0	49427	0	0
T11	31292	31291	0	0
T21	1	0	0	0
T22	1	0	0	0
T24	1	0	0	0
T25	1	0	0	0
T31	1	0	0	0
T32	0	38141	0	0
T34	0	32795	0	0
T35	0	56795	0	0
T36	0	43939	0	0
T37	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	115261329	115260510	0	0
T1	1244	1243	0	0
T2	3619	3618	0	0
T3	4641	4640	0	0
T4	8343	8342	0	0
T12	22135	22134	0	0
T13	771	770	0	0
T14	2640	2639	0	0
T15	1396	1395	0	0
T16	1379	1378	0	0
T17	610	609	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	60911	60092	0	0
selKnown1	942	123	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	60911	60092	0	0
T2	8	7	0	0
T3	8	7	0	0
T4	14	13	0	0
T5	2	1	0	0
T6	0	1	0	0
T12	55	54	0	0
T13	1	0	0	0
T14	1	0	0	0
T15	3	2	0	0
T16	1	0	0	0
T17	1	0	0	0
T21	0	80	0	0
T22	0	18	0	0
T24	0	4	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	123	0	0
T8	4	3	0	0
T9	4	3	0	0
T10	0	7	0	0
T23	1	0	0	0
T27	1	0	0	0
T28	1	0	0	0
T29	1	0	0	0
T36	1	0	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	4	0	0
T41	0	3	0	0
T42	0	6	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	1	0	0	0
T46	1	0	0	0
T47	1	0	0	0