Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_reg_tap.u_reg_if.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.50 90.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.50 90.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.91 97.37 94.29 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_reg_if.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.44 100.00 97.78 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : tlul_err
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5411100.00
ALWAYS571717100.00
CONT_ASSIGN9611100.00

25 logic op_full, op_partial, op_get; 26 1/1 assign op_full = (tl_i.a_opcode == PutFullData); Tests: T1 T2 T3  27 1/1 assign op_partial = (tl_i.a_opcode == PutPartialData); Tests: T1 T2 T3  28 1/1 assign op_get = (tl_i.a_opcode == Get); Tests: T1 T2 T3  29 30 // An instruction type transaction cannot be write 31 logic instr_wr_err; 32 1/1 assign instr_wr_err = prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) & Tests: T1 T2 T3  33 (op_full | op_partial); 34 35 logic instr_type_err; 36 1/1 assign instr_type_err = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type); Tests: T1 T2 T3  37 38 // Anything that doesn't fall into the permitted category, it raises an error 39 1/1 assign err_o = ~(opcode_allowed & a_config_allowed) | instr_wr_err | instr_type_err; Tests: T1 T2 T3  40 41 // opcode check 42 1/1 assign opcode_allowed = (tl_i.a_opcode == PutFullData) Tests: T1 T2 T3  43 | (tl_i.a_opcode == PutPartialData) 44 | (tl_i.a_opcode == Get); 45 46 // a channel configuration check 47 logic addr_sz_chk; // address and size alignment check 48 logic mask_chk; // inactive lane a_mask check 49 logic fulldata_chk; // PutFullData should have size match to mask 50 51 localparam bit [MW-1:0] MaskOne = 1; 52 logic [MW-1:0] mask; 53 54 1/1 assign mask = MaskOne << tl_i.a_address[SubAW-1:0]; Tests: T1 T2 T3  55 56 always_comb begin 57 1/1 addr_sz_chk = 1'b0; Tests: T1 T2 T3  58 1/1 mask_chk = 1'b0; Tests: T1 T2 T3  59 1/1 fulldata_chk = 1'b0; // Only valid when opcode is PutFullData Tests: T1 T2 T3  60 61 1/1 if (tl_i.a_valid) begin Tests: T1 T2 T3  62 1/1 unique case (tl_i.a_size) Tests: T1 T2 T3  63 'h0: begin // 1 Byte 64 1/1 addr_sz_chk = 1'b1; Tests: T1 T2 T3  65 1/1 mask_chk = ~|(tl_i.a_mask & ~mask); Tests: T1 T2 T3  66 1/1 fulldata_chk = |(tl_i.a_mask & mask); Tests: T1 T2 T3  67 end 68 69 'h1: begin // 2 Byte 70 1/1 addr_sz_chk = ~tl_i.a_address[0]; Tests: T1 T2 T3  71 // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0] 72 1/1 mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011) Tests: T1 T2 T3  73 : ~|(tl_i.a_mask & 4'b1100); 74 1/1 fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ; Tests: T1 T2 T3  75 end 76 77 'h2: begin // 4 Byte 78 1/1 addr_sz_chk = ~|tl_i.a_address[SubAW-1:0]; Tests: T1 T2 T3  79 1/1 mask_chk = 1'b1; Tests: T1 T2 T3  80 1/1 fulldata_chk = &tl_i.a_mask[3:0]; Tests: T1 T2 T3  81 end 82 83 default: begin // else 84 addr_sz_chk = 1'b0; 85 mask_chk = 1'b0; 86 fulldata_chk = 1'b0; 87 end 88 endcase 89 end else begin 90 1/1 addr_sz_chk = 1'b0; Tests: T1 T2 T3  91 1/1 mask_chk = 1'b0; Tests: T1 T2 T3  92 1/1 fulldata_chk = 1'b0; Tests: T1 T2 T3  93 end 94 end 95 96 1/1 assign a_config_allowed = addr_sz_chk Tests: T1 T2 T3 

Cond Coverage for Module : tlul_err
TotalCoveredPercent
Conditions3535100.00
Logical3535100.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT100,T101,T102
010CoveredT100,T101,T153
100CoveredT1,T2,T3

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01CoveredT117,T186,T120
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000CoveredT157,T184,T196
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT184,T117,T118
101CoveredT158,T196,T185
110CoveredT157,T196,T117
111CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T4
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

Branch Coverage for Module : tlul_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 61 8 8 100.00


61 if (tl_i.a_valid) begin -1- 62 unique case (tl_i.a_size) -2- 63 'h0: begin // 1 Byte 64 addr_sz_chk = 1'b1; ==> 65 mask_chk = ~|(tl_i.a_mask & ~mask); 66 fulldata_chk = |(tl_i.a_mask & mask); 67 end 68 69 'h1: begin // 2 Byte 70 addr_sz_chk = ~tl_i.a_address[0]; 71 // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0] 72 mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011) -3- ==> ==> 73 : ~|(tl_i.a_mask & 4'b1100); 74 fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ; -4- ==> ==> 75 end 76 77 'h2: begin // 4 Byte 78 addr_sz_chk = ~|tl_i.a_address[SubAW-1:0]; ==> 79 mask_chk = 1'b1; 80 fulldata_chk = &tl_i.a_mask[3:0]; 81 end 82 83 default: begin // else 84 addr_sz_chk = 1'b0; ==> 85 mask_chk = 1'b0; 86 fulldata_chk = 1'b0; 87 end 88 endcase 89 end else begin 90 addr_sz_chk = 1'b0; ==>

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T1,T2,T3
1 'h1 1 - Covered T1,T3,T4
1 'h1 0 - Covered T1,T2,T3
1 'h1 - 1 Covered T1,T3,T4
1 'h1 - 0 Covered T1,T2,T3
1 'h00000002 - - Covered T1,T2,T3
1 default - - Covered T158,T184,T185
0 - - - Covered T1,T2,T3


Assert Coverage for Module : tlul_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 1996 1996 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1996 1996 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T12 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0

Line Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err
Line No.TotalCoveredPercent
TOTAL201890.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN36100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN54100.00
ALWAYS571111100.00
CONT_ASSIGN9611100.00

25 logic op_full, op_partial, op_get; 26 1/1 assign op_full = (tl_i.a_opcode == PutFullData); Tests: T5 T6 T7  27 1/1 assign op_partial = (tl_i.a_opcode == PutPartialData); Tests: T5 T6 T7  28 1/1 assign op_get = (tl_i.a_opcode == Get); Tests: T5 T6 T7  29 30 // An instruction type transaction cannot be write 31 logic instr_wr_err; 32 1/1 assign instr_wr_err = prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) & Tests: T5 T6 T7  33 (op_full | op_partial); 34 35 logic instr_type_err; 36 0/1 ==> assign instr_type_err = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type); 37 38 // Anything that doesn't fall into the permitted category, it raises an error 39 1/1 assign err_o = ~(opcode_allowed & a_config_allowed) | instr_wr_err | instr_type_err; Tests: T1 T2 T3  40 41 // opcode check 42 1/1 assign opcode_allowed = (tl_i.a_opcode == PutFullData) Tests: T5 T6 T7  43 | (tl_i.a_opcode == PutPartialData) 44 | (tl_i.a_opcode == Get); 45 46 // a channel configuration check 47 logic addr_sz_chk; // address and size alignment check 48 logic mask_chk; // inactive lane a_mask check 49 logic fulldata_chk; // PutFullData should have size match to mask 50 51 localparam bit [MW-1:0] MaskOne = 1; 52 logic [MW-1:0] mask; 53 54 0/1 ==> assign mask = MaskOne << tl_i.a_address[SubAW-1:0]; 55 56 always_comb begin 57 1/1 addr_sz_chk = 1'b0; Tests: T1 T2 T3  58 1/1 mask_chk = 1'b0; Tests: T1 T2 T3  59 1/1 fulldata_chk = 1'b0; // Only valid when opcode is PutFullData Tests: T1 T2 T3  60 61 1/1 if (tl_i.a_valid) begin Tests: T1 T2 T3  62 1/1 unique case (tl_i.a_size) Tests: T5 T6 T7  63 'h0: begin // 1 Byte 64 excluded addr_sz_chk = 1'b1; Exclude Annotation: VC_COV_UNR 65 excluded mask_chk = ~|(tl_i.a_mask & ~mask); Exclude Annotation: VC_COV_UNR 66 excluded fulldata_chk = |(tl_i.a_mask & mask); Exclude Annotation: VC_COV_UNR 67 end 68 69 'h1: begin // 2 Byte 70 excluded addr_sz_chk = ~tl_i.a_address[0]; Exclude Annotation: VC_COV_UNR 71 // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0] 72 excluded mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011) Exclude Annotation: VC_COV_UNR 73 : ~|(tl_i.a_mask & 4'b1100); 74 excluded fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ; Exclude Annotation: VC_COV_UNR 75 end 76 77 'h2: begin // 4 Byte 78 1/1 addr_sz_chk = ~|tl_i.a_address[SubAW-1:0]; Tests: T5 T6 T7  79 1/1 mask_chk = 1'b1; Tests: T5 T6 T7  80 1/1 fulldata_chk = &tl_i.a_mask[3:0]; Tests: T5 T6 T7  81 end 82 83 default: begin // else 84 addr_sz_chk = 1'b0; Exclude Annotation: VC_COV_UNR 85 mask_chk = 1'b0; Exclude Annotation: VC_COV_UNR 86 fulldata_chk = 1'b0; Exclude Annotation: VC_COV_UNR 87 end 88 endcase 89 end else begin 90 1/1 addr_sz_chk = 1'b0; Tests: T1 T2 T3  91 1/1 mask_chk = 1'b0; Tests: T1 T2 T3  92 1/1 fulldata_chk = 1'b0; Tests: T1 T2 T3  93 end 94 end 95 96 1/1 assign a_config_allowed = addr_sz_chk Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTestsExclude Annotation
000CoveredT5,T6,T7
001Excluded VC_COV_UNR
010Excluded VC_COV_UNR
100CoveredT1,T2,T3

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTestsExclude Annotation
000Excluded VC_COV_UNR
001CoveredT5,T6,T7
010Excluded VC_COV_UNR
100CoveredT5,T6,T7

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1Excluded VC_COV_UNR

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1Excluded VC_COV_UNR

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT5,T6,T7

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTestsExclude Annotation
000CoveredT5,T6,T7
001CoveredT5,T6,T7
010Excluded VC_COV_UNR
100CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 61 2 2 100.00


61 if (tl_i.a_valid) begin -1- 62 unique case (tl_i.a_size) -2- 63 'h0: begin // 1 Byte 64 addr_sz_chk = 1'b1; ==> (Excluded) Exclude Annotation: VC_COV_UNR 65 mask_chk = ~|(tl_i.a_mask & ~mask); 66 fulldata_chk = |(tl_i.a_mask & mask); 67 end 68 69 'h1: begin // 2 Byte 70 addr_sz_chk = ~tl_i.a_address[0]; 71 // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0] 72 mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011) -3- ==> (Excluded) ==> (Excluded) 73 : ~|(tl_i.a_mask & 4'b1100); 74 fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ; -4- ==> (Excluded) ==> (Excluded) 75 end 76 77 'h2: begin // 4 Byte 78 addr_sz_chk = ~|tl_i.a_address[SubAW-1:0]; ==> 79 mask_chk = 1'b1; 80 fulldata_chk = &tl_i.a_mask[3:0]; 81 end 82 83 default: begin // else 84 addr_sz_chk = 1'b0; ==> (Excluded) Exclude Annotation: VC_COV_UNR 85 mask_chk = 1'b0; 86 fulldata_chk = 1'b0; 87 end 88 endcase 89 end else begin 90 addr_sz_chk = 1'b0; ==>

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 'h0 - - Excluded VC_COV_UNR
1 'h1 1 - Excluded VC_COV_UNR
1 'h1 0 - Excluded VC_COV_UNR
1 'h1 - 1 Excluded VC_COV_UNR
1 'h1 - 0 Excluded VC_COV_UNR
1 'h00000002 - - Covered T5,T6,T7
1 default - - Excluded VC_COV_UNR
0 - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 998 998 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 998 998 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5411100.00
ALWAYS571717100.00
CONT_ASSIGN9611100.00

25 logic op_full, op_partial, op_get; 26 1/1 assign op_full = (tl_i.a_opcode == PutFullData); Tests: T1 T2 T3  27 1/1 assign op_partial = (tl_i.a_opcode == PutPartialData); Tests: T1 T2 T3  28 1/1 assign op_get = (tl_i.a_opcode == Get); Tests: T1 T2 T3  29 30 // An instruction type transaction cannot be write 31 logic instr_wr_err; 32 1/1 assign instr_wr_err = prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) & Tests: T1 T2 T3  33 (op_full | op_partial); 34 35 logic instr_type_err; 36 1/1 assign instr_type_err = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type); Tests: T1 T2 T3  37 38 // Anything that doesn't fall into the permitted category, it raises an error 39 1/1 assign err_o = ~(opcode_allowed & a_config_allowed) | instr_wr_err | instr_type_err; Tests: T1 T2 T3  40 41 // opcode check 42 1/1 assign opcode_allowed = (tl_i.a_opcode == PutFullData) Tests: T1 T2 T3  43 | (tl_i.a_opcode == PutPartialData) 44 | (tl_i.a_opcode == Get); 45 46 // a channel configuration check 47 logic addr_sz_chk; // address and size alignment check 48 logic mask_chk; // inactive lane a_mask check 49 logic fulldata_chk; // PutFullData should have size match to mask 50 51 localparam bit [MW-1:0] MaskOne = 1; 52 logic [MW-1:0] mask; 53 54 1/1 assign mask = MaskOne << tl_i.a_address[SubAW-1:0]; Tests: T1 T2 T3  55 56 always_comb begin 57 1/1 addr_sz_chk = 1'b0; Tests: T1 T2 T3  58 1/1 mask_chk = 1'b0; Tests: T1 T2 T3  59 1/1 fulldata_chk = 1'b0; // Only valid when opcode is PutFullData Tests: T1 T2 T3  60 61 1/1 if (tl_i.a_valid) begin Tests: T1 T2 T3  62 1/1 unique case (tl_i.a_size) Tests: T1 T2 T3  63 'h0: begin // 1 Byte 64 1/1 addr_sz_chk = 1'b1; Tests: T1 T2 T3  65 1/1 mask_chk = ~|(tl_i.a_mask & ~mask); Tests: T1 T2 T3  66 1/1 fulldata_chk = |(tl_i.a_mask & mask); Tests: T1 T2 T3  67 end 68 69 'h1: begin // 2 Byte 70 1/1 addr_sz_chk = ~tl_i.a_address[0]; Tests: T1 T2 T3  71 // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0] 72 1/1 mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011) Tests: T1 T2 T3  73 : ~|(tl_i.a_mask & 4'b1100); 74 1/1 fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ; Tests: T1 T2 T3  75 end 76 77 'h2: begin // 4 Byte 78 1/1 addr_sz_chk = ~|tl_i.a_address[SubAW-1:0]; Tests: T1 T2 T3  79 1/1 mask_chk = 1'b1; Tests: T1 T2 T3  80 1/1 fulldata_chk = &tl_i.a_mask[3:0]; Tests: T1 T2 T3  81 end 82 83 default: begin // else 84 addr_sz_chk = 1'b0; 85 mask_chk = 1'b0; 86 fulldata_chk = 1'b0; 87 end 88 endcase 89 end else begin 90 1/1 addr_sz_chk = 1'b0; Tests: T1 T2 T3  91 1/1 mask_chk = 1'b0; Tests: T1 T2 T3  92 1/1 fulldata_chk = 1'b0; Tests: T1 T2 T3  93 end 94 end 95 96 1/1 assign a_config_allowed = addr_sz_chk Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err
TotalCoveredPercent
Conditions3535100.00
Logical3535100.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT100,T101,T102
010CoveredT100,T101,T153
100CoveredT1,T2,T4

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01CoveredT117,T186,T120
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000CoveredT157,T184,T196
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT184,T117,T118
101CoveredT158,T196,T185
110CoveredT157,T196,T117
111CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T4
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 61 8 8 100.00


61 if (tl_i.a_valid) begin -1- 62 unique case (tl_i.a_size) -2- 63 'h0: begin // 1 Byte 64 addr_sz_chk = 1'b1; ==> 65 mask_chk = ~|(tl_i.a_mask & ~mask); 66 fulldata_chk = |(tl_i.a_mask & mask); 67 end 68 69 'h1: begin // 2 Byte 70 addr_sz_chk = ~tl_i.a_address[0]; 71 // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0] 72 mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011) -3- ==> ==> 73 : ~|(tl_i.a_mask & 4'b1100); 74 fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ; -4- ==> ==> 75 end 76 77 'h2: begin // 4 Byte 78 addr_sz_chk = ~|tl_i.a_address[SubAW-1:0]; ==> 79 mask_chk = 1'b1; 80 fulldata_chk = &tl_i.a_mask[3:0]; 81 end 82 83 default: begin // else 84 addr_sz_chk = 1'b0; ==> 85 mask_chk = 1'b0; 86 fulldata_chk = 1'b0; 87 end 88 endcase 89 end else begin 90 addr_sz_chk = 1'b0; ==>

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T1,T2,T3
1 'h1 1 - Covered T1,T3,T4
1 'h1 0 - Covered T1,T2,T3
1 'h1 - 1 Covered T1,T3,T4
1 'h1 - 0 Covered T1,T2,T3
1 'h00000002 - - Covered T1,T2,T3
1 default - - Covered T158,T184,T185
0 - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 998 998 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 998 998 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%