Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1617866	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1830381

1

T1

912

T2

749

T3

816

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3112385	1			T1	989		T2	521		T3	676
values[0x0]	167773	1			T1	270		T2	268		T3	304
values[0x1]	168089	1			T1	258		T2	292		T3	272

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1285056	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2163191

1

T1

1047

T2

838

T3

911

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13243	1			T2	4		T3	2		T11	3
valid_sources[0x01]	9669	1			T2	12		T3	5		T12	11
valid_sources[0x02]	11334	1			T2	4		T3	9		T12	3
valid_sources[0x03]	9632	1			T2	2		T3	7		T12	3
valid_sources[0x04]	9846	1			T2	6		T3	2		T11	9
valid_sources[0x05]	24658	1			T2	1		T3	5		T11	14
valid_sources[0x06]	9608	1			T2	6		T3	3		T11	1
valid_sources[0x07]	9968	1			T3	4		T11	2		T12	4
valid_sources[0x08]	9385	1			T3	7		T11	10		T13	2
valid_sources[0x09]	8980	1			T2	28		T3	4		T11	1
valid_sources[0x0a]	9604	1			T2	8		T3	7		T11	1
valid_sources[0x0b]	9578	1			T2	1		T3	2		T11	10
valid_sources[0x0c]	9733	1			T2	3		T3	1		T11	4
valid_sources[0x0d]	11324	1			T3	10		T12	4		T13	2
valid_sources[0x0e]	10683	1			T2	1		T3	5		T13	2
valid_sources[0x0f]	12857	1			T3	4		T12	8		T13	9
valid_sources[0x10]	10639	1			T2	8		T3	1		T12	7
valid_sources[0x11]	9604	1			T2	4		T3	8		T11	9
valid_sources[0x12]	9704	1			T3	7		T11	3		T12	2
valid_sources[0x13]	9750	1			T2	2		T3	4		T11	3
valid_sources[0x14]	9809	1			T2	4		T3	3		T11	11
valid_sources[0x15]	13209	1			T2	10		T3	3		T11	8
valid_sources[0x16]	9827	1			T2	16		T3	6		T11	2
valid_sources[0x17]	9730	1			T2	2		T3	2		T11	19
valid_sources[0x18]	9878	1			T2	1		T3	4		T11	2
valid_sources[0x19]	91165	1			T2	5		T3	4		T11	2
valid_sources[0x1a]	45183	1			T2	12		T3	3		T11	8
valid_sources[0x1b]	9847	1			T2	6		T3	7		T11	1
valid_sources[0x1c]	9779	1			T2	4		T3	3		T11	12
valid_sources[0x1d]	12577	1			T2	3		T3	2		T11	2
valid_sources[0x1e]	9617	1			T2	1		T3	4		T12	1
valid_sources[0x1f]	13140	1			T3	2		T12	1		T18	2
valid_sources[0x20]	10146	1			T2	14		T3	3		T11	3
valid_sources[0x21]	9553	1			T2	8		T3	5		T11	5
valid_sources[0x22]	9187	1			T3	5		T11	1		T12	2
valid_sources[0x23]	9454	1			T2	5		T3	5		T11	2
valid_sources[0x24]	12686	1			T2	19		T3	2		T11	10
valid_sources[0x25]	9897	1			T3	4		T11	1		T12	3
valid_sources[0x26]	11099	1			T2	1		T3	2		T11	5
valid_sources[0x27]	10963	1			T2	1		T3	9		T11	9
valid_sources[0x28]	10245	1			T2	5		T3	7		T11	4
valid_sources[0x29]	9339	1			T2	4		T3	7		T11	3
valid_sources[0x2a]	9215	1			T3	3		T11	12		T12	1
valid_sources[0x2b]	11804	1			T2	4		T3	3		T11	8
valid_sources[0x2c]	9465	1			T2	4		T3	3		T11	4
valid_sources[0x2d]	14317	1			T2	2		T3	4		T11	2
valid_sources[0x2e]	28832	1			T2	1		T3	2		T11	11
valid_sources[0x2f]	9061	1			T2	3		T3	3		T13	2
valid_sources[0x30]	9281	1			T3	5		T12	4		T13	1
valid_sources[0x31]	9661	1			T2	3		T3	7		T11	12
valid_sources[0x32]	9427	1			T3	6		T11	3		T12	5
valid_sources[0x33]	9512	1			T2	11		T3	5		T11	6
valid_sources[0x34]	9528	1			T2	7		T3	2		T11	3
valid_sources[0x35]	11322	1			T2	4		T11	2		T12	2
valid_sources[0x36]	21144	1			T2	3		T3	8		T11	3
valid_sources[0x37]	9351	1			T2	3		T3	5		T11	4
valid_sources[0x38]	11830	1			T2	1		T3	2		T11	1
valid_sources[0x39]	9479	1			T2	2		T3	4		T11	3
valid_sources[0x3a]	10502	1			T3	2		T11	7		T12	1
valid_sources[0x3b]	11760	1			T2	7		T3	12		T11	9
valid_sources[0x3c]	9484	1			T3	3		T11	2		T12	5
valid_sources[0x3d]	9734	1			T2	15		T3	4		T11	1
valid_sources[0x3e]	9652	1			T2	2		T3	11		T11	2
valid_sources[0x3f]	10571	1			T2	6		T3	5		T11	2
valid_sources[0x40]	9920	1			T3	1		T11	10		T12	5
valid_sources[0x41]	9874	1			T2	9		T3	5		T11	3
valid_sources[0x42]	9941	1			T2	1		T3	3		T11	6
valid_sources[0x43]	10655	1			T3	7		T11	1		T12	5
valid_sources[0x44]	9650	1			T2	15		T3	2		T11	1
valid_sources[0x45]	10172	1			T3	2		T12	6		T13	3
valid_sources[0x46]	9265	1			T3	4		T11	7		T12	4
valid_sources[0x47]	9324	1			T2	4		T3	5		T12	2
valid_sources[0x48]	12558	1			T2	5		T3	4		T11	2
valid_sources[0x49]	10665	1			T2	5		T3	6		T11	7
valid_sources[0x4a]	9254	1			T2	2		T3	2		T11	2
valid_sources[0x4b]	11479	1			T2	1		T3	3		T11	12
valid_sources[0x4c]	18102	1			T3	7		T12	9		T13	9
valid_sources[0x4d]	9886	1			T3	7		T11	19		T12	1
valid_sources[0x4e]	9123	1			T2	2		T3	2		T12	8
valid_sources[0x4f]	10989	1			T2	4		T3	4		T11	1
valid_sources[0x50]	11010	1			T2	7		T3	7		T11	1
valid_sources[0x51]	10711	1			T2	4		T3	8		T11	2
valid_sources[0x52]	9850	1			T2	3		T3	7		T11	4
valid_sources[0x53]	9429	1			T2	2		T3	5		T11	1
valid_sources[0x54]	9674	1			T2	2		T3	7		T11	3
valid_sources[0x55]	11713	1			T3	6		T11	2		T12	2
valid_sources[0x56]	9996	1			T2	5		T3	13		T11	2
valid_sources[0x57]	10045	1			T3	3		T11	2		T12	3
valid_sources[0x58]	9186	1			T3	8		T11	10		T12	7
valid_sources[0x59]	9513	1			T2	1		T3	8		T11	2
valid_sources[0x5a]	12650	1			T3	5		T11	17		T12	2
valid_sources[0x5b]	9684	1			T3	2		T11	5		T12	5
valid_sources[0x5c]	11520	1			T2	6		T3	7		T11	7
valid_sources[0x5d]	17447	1			T2	5		T3	5		T11	1
valid_sources[0x5e]	9822	1			T3	2		T11	5		T12	4
valid_sources[0x5f]	9858	1			T2	2		T3	5		T11	3
valid_sources[0x60]	9640	1			T2	19		T3	5		T11	1
valid_sources[0x61]	9552	1			T2	2		T3	2		T11	4
valid_sources[0x62]	9771	1			T2	10		T3	5		T11	1
valid_sources[0x63]	9665	1			T2	4		T3	3		T11	3
valid_sources[0x64]	9458	1			T2	2		T3	8		T11	3
valid_sources[0x65]	9478	1			T3	4		T11	2		T12	2
valid_sources[0x66]	9566	1			T2	2		T3	6		T11	6
valid_sources[0x67]	10046	1			T3	8		T11	1		T12	4
valid_sources[0x68]	70630	1			T3	4		T11	11		T12	2
valid_sources[0x69]	9412	1			T2	1		T3	6		T12	4
valid_sources[0x6a]	11058	1			T3	8		T11	2		T12	8
valid_sources[0x6b]	9472	1			T3	2		T11	1		T12	12
valid_sources[0x6c]	10882	1			T3	3		T11	15		T12	11
valid_sources[0x6d]	9950	1			T2	5		T3	3		T11	1
valid_sources[0x6e]	9850	1			T2	18		T3	7		T12	9
valid_sources[0x6f]	13468	1			T2	9		T3	2		T11	12
valid_sources[0x70]	10067	1			T3	2		T11	4		T12	2
valid_sources[0x71]	9497	1			T2	7		T3	7		T11	1
valid_sources[0x72]	9713	1			T3	6		T11	3		T12	6
valid_sources[0x73]	9706	1			T3	5		T12	7		T18	3
valid_sources[0x74]	16011	1			T2	9		T3	10		T11	2
valid_sources[0x75]	11276	1			T2	7		T3	3		T11	4
valid_sources[0x76]	9834	1			T2	5		T3	8		T11	1
valid_sources[0x77]	10116	1			T2	3		T3	9		T11	5
valid_sources[0x78]	9796	1			T2	2		T3	6		T12	1
valid_sources[0x79]	10036	1			T2	3		T3	2		T11	6
valid_sources[0x7a]	9502	1			T2	2		T3	3		T11	1
valid_sources[0x7b]	11598	1			T2	2		T3	6		T11	12
valid_sources[0x7c]	9345	1			T3	5		T11	8		T12	1
valid_sources[0x7d]	12374	1			T3	5		T11	11		T12	4
valid_sources[0x7e]	9300	1			T2	9		T3	8		T11	2
valid_sources[0x7f]	9640	1			T3	2		T12	1		T13	2
valid_sources[0x80]	9905	1			T2	7		T3	1		T11	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1540837

1

T1

451

T2

256

T3

317

values[0x0]

all_enables

biggest_size

145637

1

T1

245

T2

239

T3

261

values[0x1]

all_enables

biggest_size

143907

1

T1

216

T2

254

T3

238