Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95133850	14236	0	0
claim_transition_if_regwen_rd_A	95133850	1839	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95133850	14236	0	0
T23	128595	2	0	0
T24	210843	0	0	0
T36	19677	0	0	0
T37	2557	0	0	0
T38	28012	0	0	0
T39	534411	0	0	0
T40	6956	0	0	0
T52	0	11	0	0
T55	0	9	0	0
T68	3103	0	0	0
T90	0	7	0	0
T96	0	4	0	0
T97	23007	0	0	0
T99	0	4	0	0
T106	0	4	0	0
T156	0	5	0	0
T157	0	4	0	0
T158	0	6	0	0
T159	2641	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95133850	1839	0	0
T34	15132	0	0	0
T83	142469	0	0	0
T99	353868	3	0	0
T100	28724	0	0	0
T101	22444	0	0	0
T102	38709	0	0	0
T103	43316	0	0	0
T104	150318	0	0	0
T105	1109	0	0	0
T106	309560	0	0	0
T123	0	1	0	0
T130	0	24	0	0
T133	0	157	0	0
T137	0	44	0	0
T142	0	39	0	0
T149	0	34	0	0
T160	0	8	0	0
T161	0	22	0	0
T162	0	28	0	0