LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.350s	666.429us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.080s	35.970us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	55.158us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.790s	50.061us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.680s	136.957us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.380s	29.928us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	55.158us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	136.957us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.450s	100.167us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.550s	2.613ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	11.986us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.070s	108.387us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	33.860s	1.049ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.420s	1.025ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	33.860s	1.049ms	50	50	100.00
		lc_ctrl_prog_failure	5.070s	108.387us	50	50	100.00
		lc_ctrl_errors	28.420s	1.025ms	49	50	98.00
		lc_ctrl_security_escalation	16.990s	1.786ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.849m	48.612ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.990s	2.241ms	20	20	100.00
		lc_ctrl_jtag_errors	2.388m	91.295ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.500s	973.516us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	21.720s	1.133ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.990s	2.241ms	20	20	100.00
		lc_ctrl_jtag_errors	2.388m	91.295ms	19	20	95.00
		lc_ctrl_jtag_access	23.440s	1.990ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.360s	1.340ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.520s	186.918us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.610s	135.658us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	22.220s	3.868ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	25.560s	4.961ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.010s	105.492us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.190s	118.375us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.060s	64.559us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.340s	1.603ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.510s	48.640us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	10.146m	68.600ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.590s	37.875us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.930s	568.397us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.930s	568.397us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.080s	35.970us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	55.158us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	136.957us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.020s	49.961us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.080s	35.970us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	55.158us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	136.957us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.020s	49.961us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	39.860s	213.226us	5	5	100.00
		lc_ctrl_tl_intg_err	4.370s	509.911us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.370s	509.911us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.550s	2.613ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	33.860s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	39.860s	213.226us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	33.860s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	39.860s	213.226us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	33.860s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	39.860s	213.226us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	33.860s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	39.860s	213.226us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	33.860s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	39.860s	213.226us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	33.860s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	39.860s	213.226us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	33.860s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	39.860s	213.226us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	33.860s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	39.860s	213.226us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.990s	1.786ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.450s	100.167us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	21.720s	1.133ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.570s	753.529us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.570s	753.529us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.770s	1.291ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.230s	3.098ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.230s	3.098ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	32.456m	295.055ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			998	1030	96.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	24	88.89
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	97.89	95.95	93.31	100.00	98.55	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.110020056180477001213744694873106972233877728331904895980097636750164568958081
      Line 4653, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6407655774 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6407655774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.18744743942454364983144009031121579338663950315748806225223270700099592231223
      Line 16686, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14415896690 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14415896690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 22.lc_ctrl_stress_all_with_rand_reset.81498122791784645655927033159390698556423138422663997909311018173693514781932
      Line 8582, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8192103602 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8192103602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.lc_ctrl_stress_all_with_rand_reset.49270684216545466967225718732330241256482914568402691614855823883666481454784
      Line 14909, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10975122178 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 10975122178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 2.lc_ctrl_jtag_errors.32753809290662303543615140876089083888479490756923765262058940154210874487693
      Line 2712, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 1454512685 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1454512685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_errors has 1 failures.

    • 40.lc_ctrl_errors.51758544356469156661179018844036770640839056904002947076713084804085585419365
      Line 1605, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 150373235 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 150373235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 29.lc_ctrl_stress_all_with_rand_reset.52261365181983625435868717277883595241749902548746858302060845804133325204560
      Line 16160, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 50516102001 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 50516102001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.lc_ctrl_stress_all_with_rand_reset.65144434835006225250456098727063434787020875780259006793970198587159421942410
      Line 17392, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 56177644805 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 56177644805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*) == * has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 35.lc_ctrl_volatile_unlock_smoke.44303429023603093659951365514395923848829485321171470358607864141056294881736
      Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 110797315 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0x2a791e04) == 0x1
        UVM_INFO @ 110797315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.22700146087525192294157811898040708008753808113068533776536673015742175663462
      Line 31567, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.04.22_07.25.13