Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1780169	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2003079

1

T1

10

T10

5

T4

136

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3431240	1			T4	113		T5	12836		T12	2536
values[0x0]	175653	1			T1	18		T10	8		T4	52
values[0x1]	176355	1			T1	20		T10	8		T4	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1414819	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2368429

1

T1

15

T10

8

T4

155

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14449	1			T5	41		T12	17		T15	17
valid_sources[0x01]	12506	1			T5	53		T12	14		T16	31
valid_sources[0x02]	12082	1			T5	56		T12	10		T16	3
valid_sources[0x03]	12282	1			T5	58		T12	12		T7	1
valid_sources[0x04]	12483	1			T5	67		T12	15		T16	2
valid_sources[0x05]	12849	1			T5	65		T12	12		T14	1
valid_sources[0x06]	12933	1			T5	90		T12	4		T14	2
valid_sources[0x07]	12324	1			T5	75		T12	10		T14	1
valid_sources[0x08]	15065	1			T5	93		T12	13		T6	1
valid_sources[0x09]	12230	1			T5	30		T12	13		T16	5
valid_sources[0x0a]	12412	1			T5	54		T12	15		T16	1
valid_sources[0x0b]	12762	1			T5	61		T12	17		T14	2
valid_sources[0x0c]	13947	1			T5	30		T12	19		T7	2
valid_sources[0x0d]	12555	1			T5	62		T12	11		T16	3
valid_sources[0x0e]	12625	1			T5	61		T12	9		T7	3
valid_sources[0x0f]	12638	1			T5	55		T12	10		T16	3
valid_sources[0x10]	12481	1			T5	35		T12	13		T16	2
valid_sources[0x11]	12673	1			T5	59		T12	7		T16	1
valid_sources[0x12]	12445	1			T5	55		T12	16		T16	1
valid_sources[0x13]	13653	1			T5	25		T12	13		T16	12
valid_sources[0x14]	101843	1			T5	96		T12	10		T6	1
valid_sources[0x15]	12282	1			T5	73		T12	8		T7	1
valid_sources[0x16]	12557	1			T5	43		T12	19		T14	2
valid_sources[0x17]	14187	1			T5	83		T12	18		T14	2
valid_sources[0x18]	14269	1			T5	50		T12	8		T16	5
valid_sources[0x19]	12356	1			T5	60		T12	17		T14	3
valid_sources[0x1a]	12508	1			T5	51		T12	11		T16	6
valid_sources[0x1b]	12324	1			T5	55		T12	16		T14	1
valid_sources[0x1c]	14284	1			T5	28		T12	16		T7	4
valid_sources[0x1d]	12443	1			T5	84		T12	13		T7	1
valid_sources[0x1e]	12373	1			T5	45		T12	16		T16	2
valid_sources[0x1f]	13719	1			T5	4		T12	16		T16	4
valid_sources[0x20]	18766	1			T5	38		T12	15		T16	5
valid_sources[0x21]	12004	1			T5	77		T12	20		T16	2
valid_sources[0x22]	12556	1			T5	15		T12	9		T16	28
valid_sources[0x23]	13432	1			T5	31		T12	16		T26	2
valid_sources[0x24]	13530	1			T5	49		T12	14		T14	1
valid_sources[0x25]	12471	1			T5	47		T12	15		T33	1
valid_sources[0x26]	14130	1			T5	104		T12	13		T16	4
valid_sources[0x27]	13158	1			T1	13		T5	49		T12	10
valid_sources[0x28]	14806	1			T5	36		T12	10		T33	1
valid_sources[0x29]	12373	1			T5	81		T12	10		T14	1
valid_sources[0x2a]	12634	1			T5	33		T12	19		T7	1
valid_sources[0x2b]	12218	1			T5	111		T12	12		T16	5
valid_sources[0x2c]	18664	1			T5	68		T12	15		T15	17
valid_sources[0x2d]	12249	1			T5	57		T12	13		T16	6
valid_sources[0x2e]	11752	1			T5	41		T12	9		T6	1
valid_sources[0x2f]	15481	1			T5	51		T12	9		T15	17
valid_sources[0x30]	25407	1			T5	11		T12	16		T14	1
valid_sources[0x31]	12495	1			T5	63		T12	20		T26	3
valid_sources[0x32]	12320	1			T5	56		T12	5		T7	1
valid_sources[0x33]	12531	1			T5	65		T12	12		T16	4
valid_sources[0x34]	12177	1			T5	61		T12	11		T16	2
valid_sources[0x35]	12354	1			T4	201		T5	54		T12	11
valid_sources[0x36]	12339	1			T5	45		T12	7		T14	2
valid_sources[0x37]	13537	1			T5	33		T12	12		T6	1
valid_sources[0x38]	17426	1			T5	71		T12	15		T16	4
valid_sources[0x39]	12633	1			T5	38		T12	13		T14	1
valid_sources[0x3a]	42665	1			T5	7		T12	11		T16	8
valid_sources[0x3b]	12127	1			T5	63		T12	10		T16	13
valid_sources[0x3c]	15125	1			T5	126		T12	12		T15	17
valid_sources[0x3d]	12873	1			T5	20		T12	17		T16	16
valid_sources[0x3e]	13531	1			T5	56		T12	5		T14	1
valid_sources[0x3f]	12722	1			T5	56		T12	16		T33	1
valid_sources[0x40]	13789	1			T5	43		T12	17		T16	8
valid_sources[0x41]	12254	1			T5	48		T12	21		T16	2
valid_sources[0x42]	12868	1			T5	85		T12	12		T16	9
valid_sources[0x43]	13152	1			T5	22		T12	8		T16	7
valid_sources[0x44]	18146	1			T5	59		T12	9		T16	12
valid_sources[0x45]	12337	1			T5	31		T12	14		T14	1
valid_sources[0x46]	13298	1			T5	46		T12	17		T14	1
valid_sources[0x47]	12281	1			T5	67		T12	5		T14	1
valid_sources[0x48]	12095	1			T5	22		T12	18		T16	9
valid_sources[0x49]	12616	1			T5	64		T12	15		T16	2
valid_sources[0x4a]	12693	1			T5	118		T12	9		T16	10
valid_sources[0x4b]	18367	1			T5	73		T12	14		T16	28
valid_sources[0x4c]	12626	1			T5	59		T12	6		T16	1
valid_sources[0x4d]	12369	1			T5	96		T12	20		T26	10
valid_sources[0x4e]	12938	1			T5	85		T12	6		T16	1
valid_sources[0x4f]	13613	1			T5	63		T12	14		T16	13
valid_sources[0x50]	12519	1			T5	42		T12	6		T14	2
valid_sources[0x51]	12416	1			T5	18		T12	21		T26	1
valid_sources[0x52]	12393	1			T5	68		T12	14		T14	1
valid_sources[0x53]	12120	1			T5	60		T12	11		T16	3
valid_sources[0x54]	13914	1			T5	29		T12	14		T16	3
valid_sources[0x55]	12943	1			T5	82		T12	14		T16	4
valid_sources[0x56]	12936	1			T5	40		T12	12		T16	1
valid_sources[0x57]	13647	1			T5	74		T12	12		T14	2
valid_sources[0x58]	12592	1			T5	57		T12	12		T14	1
valid_sources[0x59]	12396	1			T10	16		T5	93		T12	17
valid_sources[0x5a]	12817	1			T5	28		T12	10		T26	6
valid_sources[0x5b]	13044	1			T5	22		T12	13		T26	11
valid_sources[0x5c]	12668	1			T5	47		T12	9		T7	3
valid_sources[0x5d]	12687	1			T5	38		T12	14		T16	2
valid_sources[0x5e]	12550	1			T5	38		T12	10		T16	8
valid_sources[0x5f]	12978	1			T5	80		T12	6		T16	19
valid_sources[0x60]	13554	1			T1	3		T5	26		T12	17
valid_sources[0x61]	12487	1			T5	48		T12	6		T16	17
valid_sources[0x62]	12190	1			T5	59		T12	15		T26	2
valid_sources[0x63]	13104	1			T5	110		T12	16		T14	2
valid_sources[0x64]	13376	1			T1	20		T5	79		T12	10
valid_sources[0x65]	16653	1			T5	71		T12	12		T16	4
valid_sources[0x66]	11920	1			T5	67		T12	23		T7	1
valid_sources[0x67]	12193	1			T5	53		T12	8		T7	1
valid_sources[0x68]	12451	1			T5	57		T12	13		T16	12
valid_sources[0x69]	12564	1			T5	47		T12	19		T16	1
valid_sources[0x6a]	12364	1			T5	48		T12	9		T7	1
valid_sources[0x6b]	12443	1			T5	37		T12	12		T16	10
valid_sources[0x6c]	12642	1			T5	60		T12	20		T16	1
valid_sources[0x6d]	12512	1			T5	50		T12	15		T14	1
valid_sources[0x6e]	12378	1			T5	75		T12	15		T6	1
valid_sources[0x6f]	12506	1			T5	31		T12	11		T14	1
valid_sources[0x70]	19227	1			T5	36		T12	20		T16	2
valid_sources[0x71]	14402	1			T5	40		T12	7		T14	1
valid_sources[0x72]	12327	1			T5	47		T12	10		T14	1
valid_sources[0x73]	12186	1			T5	58		T12	10		T16	5
valid_sources[0x74]	14410	1			T5	66		T12	19		T14	1
valid_sources[0x75]	12358	1			T5	26		T12	10		T16	8
valid_sources[0x76]	12651	1			T1	2		T5	53		T12	9
valid_sources[0x77]	14329	1			T5	40		T12	6		T18	974
valid_sources[0x78]	15473	1			T5	25		T12	11		T14	1
valid_sources[0x79]	12478	1			T5	92		T12	17		T16	2
valid_sources[0x7a]	12871	1			T5	52		T12	11		T16	2
valid_sources[0x7b]	14285	1			T5	70		T12	17		T16	5
valid_sources[0x7c]	14314	1			T5	50		T12	20		T16	3
valid_sources[0x7d]	12485	1			T5	45		T12	15		T16	2
valid_sources[0x7e]	12538	1			T5	76		T12	14		T7	1
valid_sources[0x7f]	12264	1			T5	36		T12	10		T16	12
valid_sources[0x80]	12957	1			T5	83		T12	9		T13	369

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1699676

1

T4

56

T5

6228

T12

1289

values[0x0]

all_enables

biggest_size

152411

1

T1

6

T10

2

T4

46

values[0x1]

all_enables

biggest_size

150992

1

T1

4

T10

3

T4

34